2008 |
54 | EE | Michael Yap San Min,
Philippe Maurine,
Magali Bastian,
Michel Robert:
A Novel Dummy Bitline Driver for Read Margin Improvement in an eSRAM.
DELTA 2008: 107-110 |
53 | EE | Nicolas Saint-Jean,
Gilles Sassatelli,
Pascal Benoit,
Lionel Torres,
Michel Robert:
Bio-inspiration helps computers: A new machine.
FPL 2008: 697-698 |
52 | | Olivier Brousse,
Gilles Sassatelli,
Thierry Gil,
Yoann Guillemenet,
Michel Robert,
François Grize,
Eduardo Sanchez,
Yann Thoma,
Andres Upegui,
Juan Manuel Moreno,
Jordi Madrenas:
BAF: A Bio-Inspired Agent Framework for Distributed Pervasive Applications.
GEM 2008: 115-121 |
51 | EE | Olivier Brousse,
Gilles Sassatelli,
Thierry Gil,
Michel Robert,
François Grize,
Eduardo Sanchez,
Andres Upegui,
Yann Thoma:
The Perplexus Programming Framework: Combining Bio-inspiration and Agent-Oriented Programming for the Simulation of Large Scale Complex Systems.
ICES 2008: 402-407 |
50 | EE | Nicolas Saint-Jean,
Pascal Benoit,
Gilles Sassatelli,
Lionel Torres,
Michel Robert:
MPI-Based Adaptive Task Migration Support on the HS-Scale System.
ISVLSI 2008: 105-110 |
49 | EE | Michael Yap San Min,
Philippe Maurine,
Magali Bastian,
Michel Robert:
Statistical Sizing of an eSRAM Dummy Bitline Driver for Read Margin Improvement in the Presence of Variability Aspects.
ISVLSI 2008: 310-315 |
48 | EE | Bettina Rebaud,
Marc Belleville,
Christian Bernard,
Zequin Wu,
Michel Robert,
Philippe Maurine,
Nadine Azémard:
Setup and Hold Timing Violations Induced by Process Variations, in a Digital Multiplier.
ISVLSI 2008: 316-321 |
47 | EE | Rafael Soares,
Ney Laert Vilar Calazans,
Victor Lomné,
Philippe Maurine,
Lionel Torres,
Michel Robert:
Evaluating the robustness of secure triple track logic through prototyping.
SBCCI 2008: 193-198 |
2007 |
46 | EE | Gilles Sassatelli,
Nicolas Saint-Jean,
Pascal Benoit,
Lionel Torres,
Michel Robert,
Cristiane R. Woszezenki,
Ismael Grehs,
Fernando Gehm Moraes:
Run-time mapping and communication strategies for Homogeneous NoC-Based MPSoCs.
FCCM 2007: 295-296 |
45 | EE | Nicolas Saint-Jean,
Pascal Benoit,
Gilles Sassatelli,
Lionel Torres,
Michel Robert:
Application Case Studies on HS-Scale, a MP-SOC for Embbeded Systems.
ICSAMOS 2007: 88-95 |
44 | EE | Daniel Mesquita,
Benoît Badrignans,
Lionel Torres,
Gilles Sassatelli,
Michel Robert,
Fernando Moraes:
A Cryptographic Coarse Grain Reconfigurable Architecture Robust Against DPA.
IPDPS 2007: 1-8 |
43 | EE | Nicolas Saint-Jean,
Gilles Sassatelli,
Pascal Benoit,
Lionel Torres,
Michel Robert:
HS-Scale: a Hardware-Software Scalable MP-SOC Architecture for embedded Systems.
ISVLSI 2007: 21-28 |
42 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Analysis and Improvement of Dual Rail Logic as a Countermeasure Against DPA.
PATMOS 2007: 340-351 |
41 | | Nicolas Saint-Jean,
Camille Jalier,
Gilles Sassatelli,
Pascal Benoit,
Lionel Torres,
Michel Robert:
HS Scale: A run-time adaptable MP-SoC architecture.
ReCoSoC 2007: 39-46 |
40 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Improvement of dual rail logic as a countermeasure against DPA.
VLSI-SoC 2007: 270-275 |
2006 |
39 | EE | Daniel Mesquita,
Benoît Badrignans,
Lionel Torres,
Gilles Sassatelli,
Michel Robert,
Jean-Claude Bajard,
Fernando Gehm Moraes:
A Leak Resistant Architecture Against Side Channel Attacks.
FPL 2006: 1-4 |
38 | EE | Pascal Benoit,
Lionel Torres,
Gilles Sassatelli,
Michel Robert,
Gaston Cambon,
Jürgen Becker:
Dynamic Hardware Multiplexing: Improving Adaptability with a Run Time Reconfiguration Manager.
ISVLSI 2006: 251-256 |
37 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Formal Evaluation of the Robustness of Dual-Rail Logic Against DPA Attacks.
PATMOS 2006: 634-644 |
36 | | Benoît Badrignans,
Daniel Mesquita,
Jean-Claude Bajard,
Lionel Torres,
Gilles Sassatelli,
Michel Robert:
A Parallel and Secure Architecture for Asymmetric Cryptography.
ReCoSoC 2006: 220-224 |
35 | EE | Alin Razafindraibe,
Philippe Maurine,
Michel Robert,
Marc Renaudin:
Security evaluation of dual rail logic against DPA attacks.
VLSI-SoC 2006: 181-186 |
2005 |
34 | EE | F. Gensolen,
Guy Cathebras,
Lionel Martin,
Michel Robert:
An Image Sensor with Global Motion Estimation for Micro Camera Module.
ACIVS 2005: 713-721 |
33 | EE | Pascal Benoit,
Lionel Torres,
Gilles Sassatelli,
Michel Robert,
Gaston Cambon:
Dynamic hardware multiplexing for coarse grain reconfigurable architectures.
FPGA 2005: 270 |
32 | | Pascal Benoit,
Jürgen Becker,
Michel Robert,
Lionel Torres,
Gilles Sassatelli,
Gaston Cambon:
Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors.
FPL 2005: 703-706 |
31 | EE | Pascal Benoit,
Lionel Torres,
Gilles Sassatelli,
Michel Robert,
Gaston Cambon:
Automatic Task Scheduling / Loop Unrolling using Dedicated RTR Controllers in Coarse Grain Reconfigurable Architectures.
IPDPS 2005 |
30 | EE | Alin Razafindraibe,
Michel Robert,
Marc Renaudin,
Philippe Maurine:
A Method to Design Compact Dual-rail Asynchronous Primitives.
PATMOS 2005: 571-580 |
29 | | Daniel Mesquita,
Jean-Denis Techer,
Lionel Torres,
Gilles Sassatelli,
Gaston Cambon,
Michel Robert,
Fernando Moraes:
A new hardware countermeasure for masking power signatures of crypto cores.
ReCoSoC 2005: 169-176 |
28 | EE | Daniel Mesquita,
Jean-Denis Techer,
Lionel Torres,
Gilles Sassatelli,
Gaston Cambon,
Michel Robert,
Fernando Moraes:
Current mask generation: a transistor level security against DPA attacks.
SBCCI 2005: 115-120 |
27 | EE | Daniel Mesquita,
Jean-Denis Techer,
Lionel Torres,
Michel Robert,
Guy Cathebras,
Gilles Sassatelli,
Fernando Gehm Moraes:
Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.
VLSI-SoC 2005: 317-330 |
26 | EE | Alin Razafindraibe,
Michel Robert,
Philippe Maurine:
Compact and Secured Primitives for the Design of Asynchronous Circuits.
J. Low Power Electronics 1(1): 20-26 (2005) |
25 | EE | Pascal Benoit,
Gilles Sassatelli,
Lionel Torres,
Michel Robert,
Gaston Cambon,
Didier Demigny:
Méthode de caractérisation des architectures d'accélérateurs flexibles pour systèmes sur puce.
Technique et Science Informatiques 24(6): 725-755 (2005) |
2004 |
24 | EE | Olivier Omedes,
Michel Robert,
Mohammed Ramdani:
A flexibility aware budgeting for hierarchical flow timing closure.
ICCAD 2004: 261-266 |
23 | EE | A. Landrault,
Nadine Azémard,
Philippe Maurine,
Michel Robert,
Daniel Auvergne:
Design Optimization with Automated Cell Generation.
PATMOS 2004: 722-731 |
22 | EE | Pascal Benoit,
Gilles Sassatelli,
Lionel Torres,
Didier Demigny,
Michel Robert,
Gaston Cambon:
Metrics for Digital Signal Processing Architectures Characterization: Remanence and Scalability.
SAMOS 2004: 128-137 |
2003 |
21 | EE | Pascal Benoit,
Gilles Sassatelli,
Lionel Torres,
Michel Robert,
Gaston Cambon,
Didier Demigny:
A Novel Approach for Architectural Model Characterization. An Example through the Systolic Ring.
FPL 2003: 722-732 |
20 | EE | Pascal Benoit,
Gilles Sassatelli,
Lionel Torres,
Didier Demigny,
Michel Robert,
Gaston Cambon:
Metrics for Reconfigurable Architectures Characterization: Remanence and Scalability.
IPDPS 2003: 176 |
19 | | Daniel Mesquita,
Lionel Torres,
Fernando Gehm Moraes,
Gilles Sassatelli,
Michel Robert:
Are coarse grain reconfigurable architectures suitable for cryptography?
VLSI-SOC 2003: 276-281 |
2002 |
18 | | Michel Robert,
Bruno Rouzeyre,
Christian Piguet,
Marie-Lise Flottes:
SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France
Kluwer 2002 |
17 | EE | A. Landrault,
L. Pellier,
A. Richard,
C. Jay,
Michel Robert,
Daniel Auvergne:
Transistor Level Synthesis Dedicated to Fast I.P. Prototyping.
PATMOS 2002: 156-166 |
16 | | Christel-Loic Tisse,
Lionel Martin,
Lionel Torres,
Michel Robert:
Iris recognition system for person identification.
PRIS 2002: 186-199 |
2001 |
15 | | Gilles Sassatelli,
Lionel Torres,
Pascal Benoit,
Gaston Cambon,
Michel Robert,
Jérôme Galy:
Dynamically Reconfigurable Architectures for Digital Signal Processing Applications.
VLSI-SOC 2001: 63-74 |
2000 |
14 | | Camille Diou,
Lionel Torres,
Michel Robert:
A Wavelet Core for Video Processing.
ICIP 2000 |
1999 |
13 | EE | Sébastien Pillement,
Lionel Torres,
Michel Robert,
Gaston Cambon:
Fast Prototyping: A Case Study - The JPEG Compression Algorithm.
IEEE International Workshop on Rapid System Prototyping 1999: 87- |
12 | | Michel Robert:
Increasing test coverage in a VLSI design course.
ITC 1999: 1135 |
11 | | Camille Diou,
Lionel Torres,
Michel Robert:
Implementation of a Wavelet Transform Architecture for Image Processing.
VLSI 1999: 101-112 |
10 | | Augusto Gallegos,
Philippe Silvestre,
Michel Robert,
Daniel Auvergne:
RF Interface Design Using Mixed-Mode Methodology.
VLSI 1999: 326-333 |
9 | | S. Raimbault,
Gilles Sassatelli,
Gamille Cambon,
Michel Robert,
Sébastien Pillement,
Lionel Torres:
Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies.
VLSI 1999: 407-414 |
8 | | Fernando Moraes,
Michel Robert,
Daniel Auvergne:
A Virtual CMOS Library Approach for East Layout Synthesis.
VLSI 1999: 415-426 |
1998 |
7 | EE | Lionel Torres,
El-Bay Bourennane,
Michel Robert,
Michel Paindavoine:
A Recursive Digital Filter Implementation for Noisy and Blurred Images.
Real-Time Imaging 4(3): 181-191 (1998) |
1996 |
6 | | Sébastien Pillement,
Lionel Torres,
Michel Robert,
Gaston Cambon:
Concurrent Design of Hardware/Software Dedicated Systems.
FPL 1996: 410-414 |
1995 |
5 | EE | Jean Michel Daga,
Michel Robert,
Daniel Auvergne:
Delay modelling improvement for low voltage applications.
EURO-DAC 1995: 216-221 |
1994 |
4 | | Michel Robert,
P. Gorria,
Johel Mitéran,
S. Turgis:
Design of a Real Time Geometric Classifier.
EDAC-ETC-EUROASIC 1994: 656 |
3 | | Michel Robert,
Lionel Torres,
Fernando Moraes,
Daniel Auvergne:
Influence of Locig Block Layout Architecture on FPGA Performance.
FPL 1994: 34-44 |
1993 |
2 | EE | Denis Deschacht,
Michel Robert,
Nadine Azémard-Crestani,
Daniel Auvergne:
Post-layout timing simulation of CMOS circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1170-1177 (1993) |
1990 |
1 | EE | Denis Deschacht,
P. Pinede,
Michel Robert,
Daniel Auvergne:
Path runner: an accurate and fast timing analyser.
EURO-DAC 1990: 529-533 |