| 1997 |
|---|
| 13 | | Kuan-Jen Lin,
Chi-Wen Kuo,
Chen-Shang Lin:
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph.
IEEE Trans. Computers 46(11): 1246-1263 (1997) |
| 1996 |
|---|
| 12 | EE | Chen-Pin Kung,
Chen-Shang Lin:
Parallel sequence fault simulation for synchronous sequential circuits.
J. Electronic Testing 9(3): 267-277 (1996) |
| 1995 |
|---|
| 11 | EE | Chen-Pin Kung,
Chun-Jieh Huang,
Chen-Shang Lin:
Fast fault simulation for BIST applications.
Asian Test Symposium 1995: 93-99 |
| 10 | EE | Jau-Shien Chang,
Chen-Shang Lin:
Test set compaction for combinational circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(11): 1370-1378 (1995) |
| 1994 |
|---|
| 9 | | Kuan-Jen Lin,
Jih-Wen Kuo,
Chen-Shang Lin:
Direct Synthesis of Hazard-Free Asynchronous Circuits from STGs Based on Lock Relation and BG-Decomposition Approach.
EDAC-ETC-EUROASIC 1994: 178-183 |
| 8 | EE | Chen-Pin Kung,
Chen-Shang Lin:
HyHOPE: a fast fault simulator with efficient simulation of hypertrophic faults.
ICCAD 1994: 714-718 |
| 7 | | Jau-Shien Chang,
Chen-Shang Lin:
A Test-Clock Reduction Method for Scan-Designed Circuits.
ITC 1994: 331-339 |
| 1992 |
|---|
| 6 | EE | Kuan-Jen Lin,
Chen-Shang Lin:
On the verification of state-coding in STGs.
ICCAD 1992: 118-122 |
| 5 | | Heh-Tyan Liaw,
Chen-Shang Lin:
On the OBDD-Representation of General Boolean Functions.
IEEE Trans. Computers 41(6): 661-664 (1992) |
| 1991 |
|---|
| 4 | EE | Kuan-Jen Lin,
Chen-Shang Lin:
Automatic Synthesis of Asynchronous Circuits.
DAC 1991: 296-301 |
| 1990 |
|---|
| 3 | | Heh-Tyan Liaw,
Jia-Horng Tsaih,
Chen-Shang Lin:
Efficient Automatic Diagnosis of Digital Circuits.
ICCAD 1990: 464-467 |
| 1989 |
|---|
| 2 | EE | Heh-Tyan Liaw,
K.-T. Tran,
Chen-Shang Lin:
VVDS: A Verification/Diagnosis System for VHDL.
DAC 1989: 435-440 |
| 1988 |
|---|
| 1 | EE | Chen-Shang Lin,
Hong-Fa Ho:
Automatic Functional Test Program Generation for Microprocessors.
DAC 1988: 605-608 |
