| 1999 |
|---|
| 4 | EE | Stefan Hendricx,
Luc J. M. Claesen:
Verification of Finite-State-Machine Refinements Using a Symbolic Methodology.
CHARME 1999: 326-329 |
| 3 | EE | Stefan Hendricx,
Luc J. M. Claesen:
Formally Verified Redundancy Removal.
DATE 1999: 150- |
| 2 | EE | Stefan Hendricx,
Luc J. M. Claesen:
Symbolic Multi-Level Verification of Refinement.
Great Lakes Symposium on VLSI 1999: 288-291 |
| 1997 |
|---|
| 1 | EE | Stefan Hendricx,
Luc J. M. Claesen:
A symbolic core approach to the formal verification of integrated mixed-mode applications.
ED&TC 1997: 432-436 |
