| 2006 |
|---|
| 9 | EE | Konstantinos Masselos,
Kari Tiensyrjä,
Yang Qu,
Nikos S. Voros,
Miroslav Cupák,
Luc Rijnders,
Marko Pettissalo:
System Level Architecture Exploration for Reconfigurable Systems On Chip.
FPL 2006: 1-6 |
| 2003 |
|---|
| 8 | EE | Richard Stahl,
Robert Pasko,
Luc Rijnders,
Diederik Verkest,
Serge Vernalde,
Rudy Lauwereins,
Francky Catthoor:
Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java.
SCOPES 2003: 313-328 |
| 2000 |
|---|
| 7 | EE | Yajun Ha,
Patrick Schaumont,
Marc Engels,
Serge Vernalde,
Freddy Potargent,
Luc Rijnders,
Hugo De Man:
A Hardware Virtual Machine for the Networked Reconfiguration.
IEEE International Workshop on Rapid System Prototyping 2000: 194-199 |
| 1999 |
|---|
| 6 | EE | Radim Cmar,
Luc Rijnders,
Patrick Schaumont,
Serge Vernalde,
Ivo Bolsens:
A Methodology and Design Environment for DSP ASIC Fixed-Point Refinement.
DATE 1999: 271- |
| 1998 |
|---|
| 5 | EE | Patrick Schaumont,
Serge Vernalde,
Luc Rijnders,
Marc Engels,
Ivo Bolsens:
A Programming Environment for the Design of Complex High Speed ASICs.
DAC 1998: 315-320 |
| 1997 |
|---|
| 4 | EE | Patrick Schaumont,
Serge Vernalde,
Luc Rijnders,
Marc Engels,
Ivo Bolsens:
Synthesis of multi-rate and variable rate circuits for high speed telecommunications applications.
ED&TC 1997: 542-546 |
| 1995 |
|---|
| 3 | EE | Luc Rijnders,
Zohair Sahraoui,
Paul Six,
Hugo De Man:
Timing optimization by bit-level arithmetic transformations.
EURO-DAC 1995: 48-53 |
| 1989 |
|---|
| 2 | EE | I. Vandeweerd,
Kris Croes,
Luc Rijnders,
Paul Six,
Hugo De Man:
REDUSA: Module Generation by Automatic Elimination of Superfluous Blocks in Regular Structures.
DAC 1989: 694-697 |
| 1 | EE | I. Vandeweerd,
Kris Croes,
Luc Rijnders,
Paul Six,
Hugo De Man:
REDUSA: module generation by automatic elimination of superfluous blocks in regular structures.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(9): 989-998 (1989) |
