| 1997 |
|---|
| 20 | EE | Sergey Gavrilov,
Alexey Glebov,
S. Rusakov,
David Blaauw,
Larry G. Jones,
Gopalakrishnan Vijayan:
Fast power loss calculation for digital static CMOS circuits.
ED&TC 1997: 411-415 |
| 19 | EE | Sergey Gavrilov,
Alexey Glebov,
Satyamurthy Pullela,
S. C. Moore,
Abhijit Dharchoudhury,
Rajendran Panda,
Gopalakrishnan Vijayan,
David Blaauw:
Library-less synthesis for static CMOS combinational logic circuits.
ICCAD 1997: 658-662 |
| 1995 |
|---|
| 18 | EE | Vinod Narayananan,
David LaPotin,
Rajesh K. Gupta,
Gopalakrishnan Vijayan:
PEPPER - a timing driven early floorplanner.
ICCD 1995: 230-235 |
| 1992 |
|---|
| 17 | | Pradip Bose,
David LaPotin,
Gopalakrishnan Vijayan,
Sungho Kim:
Workload-Driven Floorplanning for MIPS Optimization.
ICCD 1992: 387-391 |
| 16 | EE | Vijay S. Iyengar,
Gopalakrishnan Vijayan:
Optimized test application timing for AC test.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1439-1449 (1992) |
| 1991 |
|---|
| 15 | | Vijay S. Iyengar,
Gopalakrishnan Vijayan:
Test Application Timing: The Unexplored Issue in AC Test.
ITC 1991: 840-847 |
| 14 | EE | Ananth V. Iyer,
H. Donald Ratliff,
Gopalakrishnan Vijayan:
On an edge ranking problem of trees and graphs.
Discrete Applied Mathematics 30(1): 43-52 (1991) |
| 13 | | Gopalakrishnan Vijayan:
Generalization of Min-Cut Partitioning to Tree Structures and Its Applications.
IEEE Trans. Computers 40(3): 307-314 (1991) |
| 12 | EE | Gopalakrishnan Vijayan,
Ren-Song Tsay:
A new method for floor planning using topological constraint reduction.
IEEE Trans. on CAD of Integrated Circuits and Systems 10(12): 1494-1501 (1991) |
| 1990 |
|---|
| 11 | | Gopalakrishnan Vijayan,
Ren-Song Tsay:
Floorplanning by Topological Constraint Reduction.
ICCAD 1990: 106-109 |
| 10 | EE | Jan-Ming Ho,
Majid Sarrafzadeh,
Gopalakrishnan Vijayan,
Chak-Kuen Wong:
Layer assignment for multichip modules.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(12): 1272-1277 (1990) |
| 9 | EE | Gopalakrishnan Vijayan:
Partitioning logic on graph structures to minimize routing cost.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(12): 1326-1334 (1990) |
| 8 | EE | Jan-Ming Ho,
Gopalakrishnan Vijayan,
Chak-Kuen Wong:
New algorithms for the rectilinear Steiner tree problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 185-193 (1990) |
| 7 | EE | Jan-Ming Ho,
Majid Sarrafzadeh,
Gopalakrishnan Vijayan,
Chak-Kuen Wong:
Pad minimization for planar routing of multiple power nets.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(4): 419-426 (1990) |
| 1989 |
|---|
| 6 | EE | Jan-Ming Ho,
Gopalakrishnan Vijayan,
C. K. Wong:
A New Approach to the Rectilinear Steiner Tree Problem.
DAC 1989: 161-166 |
| 5 | EE | Gopalakrishnan Vijayan:
Min-cost Partitioning on a Tree Structure and Applications.
DAC 1989: 771-774 |
| 4 | EE | Gopalakrishnan Vijayan,
H. H. Chen,
Chak-Kuen Wong:
On VHV-routing in channels with irregular boundaries.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 146-152 (1989) |
| 1988 |
|---|
| 3 | | Ananth V. Iyer,
H. Donald Ratliff,
Gopalakrishnan Vijayan:
Optimal Node Ranking of Trees.
Inf. Process. Lett. 28(5): 225-229 (1988) |
| 1985 |
|---|
| 2 | | Gopalakrishnan Vijayan,
Avi Wigderson:
Rectilinear Graphs and their Embeddings.
SIAM J. Comput. 14(2): 355-372 (1985) |
| 1983 |
|---|
| 1 | EE | Richard J. Lipton,
Jacobo Valdes,
Gopalakrishnan Vijayan,
Stephen C. North,
Robert Sedgewick:
VLSI Layout as Programming.
ACM Trans. Program. Lang. Syst. 5(3): 405-421 (1983) |
