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Peter Lidén

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1996
9EEPeter Dahlgren, Peter Lidén: A fault model for switch-level simulation of gate-to-drain shorts. VTS 1996: 414-421
1995
8 Peter Dahlgren, Peter Lidén: A Switch-level Algorithm for Simulation of Transients in Combinational Logic. FTCS 1995: 207-216
7 Peter Lidén, Peter Dahlgren: Coverage of Transistor-Level and Gate-Level Stuck-at Faults in CMOS Checkers. ISCAS 1995: 2124-2127
6EEPeter Lidén, Peter Dahlgren: Switch-level modeling of transistor-level stuck-at faults. VTS 1995: 208-215
1994
5EEPeter Dahlgren, Peter Lidén: Modeling of Intermediate Node States in switch-Level Networks. DAC 1994: 722-727
4 Peter Lidén, Peter Dahlgren, Rolf Johansson, Johan Karlsson: On Latching Probability of Particle Induced Transients in Combinational Networks. FTCS 1994: 340-349
1993
3EEPeter Dahlgren, Peter Lidén: Efficient modeling of switch-level networks containing undetermined logic node states. ICCAD 1993: 746-752
1992
2 Peter Lidén, Peter Dahlgren, Jan Torin: Transistor Fault Coverage for Self-Testing CMOS Checkers. ITC 1992: 476-485
1991
1 Johan Karlsson, Ulf Gunneflo, Peter Lidén, Jan Torin: Two Fault Injection Techniques for Test of Fault Handling Mechanisms. ITC 1991: 140-149

Coauthor Index

1Peter Dahlgren [2] [3] [4] [5] [6] [7] [8] [9]
2Ulf Gunneflo [1]
3Rolf Johansson [4]
4Johan Karlsson [1] [4]
5Jan Torin [1] [2]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)