| 1997 |
|---|
| 3 | EE | Kazumi Hatayama,
Mitsuji Ikeda,
Masahiro Takakura,
Satoshi Uchiyama,
Yoriyuki Sakamoto:
Application of a Design for Delay Testability Approach to High Speed Logic LSIs.
Asian Test Symposium 1997: 112-115 |
| 1992 |
|---|
| 2 | | Kazumi Hatayama,
Kazunori Hikone,
Mitsuji Ikeda,
Terumine Hayashi:
Sequential Test Generation Based on Real-Value Logic.
ITC 1992: 41-48 |
| 1989 |
|---|
| 1 | | Kazumi Hatayama,
Mitsuji Ikeda,
Terumine Hayashi,
Masahiro Takakura,
Kuniaki Kishida,
Shun Ishiyama:
Enhanced Delay Test Generator for High-Speed Logic LSIs.
ITC 1989: 161-165 |
