2008 |
33 | EE | Matthew Hill,
Murray Campbell,
Yuan-Chi Chang,
Vijay S. Iyengar:
Event detection in sensor networks for modern oil fields.
DEBS 2008: 95-102 |
2007 |
32 | EE | Vijay S. Iyengar,
Ioana Boier,
Karen Kelley,
Raymond Curatolo:
Analytics for Audit and Business Controls in Corporate Travel and Entertainment.
AusDM 2007: 3-12 |
2006 |
31 | EE | Vijay S. Iyengar,
David Flaxer,
Anil Nigam,
John Vergo:
Evaluation of IT Portfolio Options by Linking to Business Services.
DEECS 2006: 66-80 |
2004 |
30 | EE | Vijay S. Iyengar:
On detecting space-time clusters.
KDD 2004: 587-592 |
2002 |
29 | EE | Vijay S. Iyengar:
Transforming data to satisfy privacy constraints.
KDD 2002: 279-288 |
28 | EE | Tong Zhang,
Vijay S. Iyengar:
Recommender Systems Using Linear Classifier.
Journal of Machine Learning Research 2: 313-334 (2002) |
2001 |
27 | EE | Vijay S. Iyengar,
Jon Lee,
Murray Campbell:
Evaluating multiple attribute items using queries.
ACM Conference on Electronic Commerce 2001: 144-153 |
26 | EE | Vijay S. Iyengar,
Tong Zhang:
Empirical Study of Recommender Systems Using Linear Classifiers.
PAKDD 2001: 16-27 |
2000 |
25 | EE | Vijay S. Iyengar,
Chidanand Apté,
Tong Zhang:
Active learning using adaptive resampling.
KDD 2000: 91-98 |
1999 |
24 | EE | Vijay S. Iyengar:
HOT: Heuristics for Oblique Trees.
ICTAI 1999: 91-98 |
1996 |
23 | EE | Vijay S. Iyengar,
Louise Trevillyan,
Pradip Bose:
Representative Traces for Processor Models with Infinite Cache.
HPCA 1996: 62-72 |
1995 |
22 | EE | Ashok K. Chandra,
Vijay S. Iyengar,
D. Jameson,
R. V. Jawalekar,
Indira Nair,
Barry K. Rosen,
Michael P. Mullen,
J. Yoon,
R. Armoni,
Daniel Geist,
Yaron Wolfsthal:
AVPGEN-A test generator for architecture verification.
IEEE Trans. VLSI Syst. 3(2): 188-200 (1995) |
1994 |
21 | | Ashok K. Chandra,
Vijay S. Iyengar,
R. V. Jawalekar,
Michael P. Mullen,
Indira Nair,
Barry K. Rosen:
Architectural Verification of Processors Using Symbolic Instruction Graphs.
ICCD 1994: 454-459 |
20 | EE | Daniel Brand,
Vijay S. Iyengar:
Identification of redundant delay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(5): 553-565 (1994) |
1992 |
19 | | Daniel Brand,
Vijay S. Iyengar:
Identification of Single Gate Delay Fault Redundancies.
ICCD 1992: 24-28 |
18 | | Ashok K. Chandra,
Vijay S. Iyengar:
Constraint Slving for Test Case Generation.
ICCD 1992: 245-248 |
17 | | Sandip Kundu,
Leendert M. Huisman,
Indira Nair,
Vijay S. Iyengar,
Lakshmi N. Reddy:
A Small Test Generator for Large Designs.
ITC 1992: 30-40 |
16 | | Yaron Aizenbud,
Paul Chang,
Moshe Leibowitz,
Dave Smith,
Bernd Könemann,
Vijay S. Iyengar,
Barry K. Rosen:
AC Test Quality: Beyond Transition Fault Coverage.
ITC 1992: 568-577 |
15 | | Bernd Könemann,
J. Barlow,
Paul Chang,
R. Gabrielson,
C. Goertz,
Brion L. Keller,
Kevin McCauley,
J. Tischer,
Vijay S. Iyengar,
Barry K. Rosen,
T. Williams:
Delay Test: The Next Frontier for LSSD Test Systems.
ITC 1992: 578-587 |
14 | EE | Vijay S. Iyengar,
Gopalakrishnan Vijayan:
Optimized test application timing for AC test.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1439-1449 (1992) |
1991 |
13 | | Vijay S. Iyengar,
Gopalakrishnan Vijayan:
Test Application Timing: The Unexplored Issue in AC Test.
ITC 1991: 840-847 |
1990 |
12 | EE | Vijay S. Iyengar,
Barry K. Rosen,
John A. Waicukauski:
On computing the sizes of detected delay faults.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(3): 299-312 (1990) |
1989 |
11 | | Daniel Brand,
Vijay S. Iyengar:
Synthesis of Pseudo-Random Pattern Testable Designs.
ITC 1989: 501-508 |
1988 |
10 | | Vijay S. Iyengar,
Barry K. Rosen,
Ilan Y. Spillinger:
Delay Test Generation 1: Concepts and Coverage Metrics.
ITC 1988: 857-866 |
9 | | Vijay S. Iyengar,
Barry K. Rosen,
Ilan Y. Spillinger:
Delay Test Generation 2: Algebra and Algorithms.
ITC 1988: 867-876 |
8 | | Daniel Brand,
Vijay S. Iyengar:
Timing Analysis Using Functional Analysis.
IEEE Trans. Computers 37(10): 1309-1315 (1988) |
7 | EE | Zeev Barzilai,
Daniel K. Beece,
Leendert M. Huisman,
Vijay S. Iyengar,
Gabriel M. Silberman:
SLS-a fast switch-level simulator [for MOS].
IEEE Trans. on CAD of Integrated Circuits and Systems 7(8): 838-849 (1988) |
1986 |
6 | EE | Zeev Barzilai,
Daniel K. Beece,
Leendert M. Huisman,
Vijay S. Iyengar,
Gabriel M. Silberman:
SLS - a fast switch level simulator for verification and fault coverage analysis.
DAC 1986: 164-170 |
5 | | Zeev Barzilai,
J. Lawrence Carter,
Vijay S. Iyengar,
Indira Nair,
Barry K. Rosen,
Joe D. Rutledge,
Gabriel M. Silberman:
Efficient Fault Simulation of CMOS Circuits with Accurate Models.
ITC 1986: 520-529 |
4 | | John A. Waicukauski,
Eric Lindbloom,
Vijay S. Iyengar,
Barry K. Rosen:
Transition Fault Simulation by Parallel Pattern Single Fault Propagation.
ITC 1986: 542-551 |
1985 |
3 | | Zeev Barzilai,
Vijay S. Iyengar,
Barry K. Rosen,
Gabriel M. Silberman:
Accurate Fault Modeling and Efficient Simulation of Differential CVS Circuits.
ITC 1985: 722-731 |
2 | | Vijay S. Iyengar,
Larry L. Kinney:
Concurrent Fault Detection in Microprogrammed Control Units.
IEEE Trans. Computers 34(9): 810-821 (1985) |
1982 |
1 | | Vijay S. Iyengar,
Larry L. Kinney:
Concurrent Testing of Flow of Control in Simple Microprogrammed Control Units.
ITC 1982: 469-479 |