| 1996 |
|---|
| 8 | EE | Najmi T. Jarwala,
Paul W. Rutkowski,
Shianling Wu,
Chi W. Yau:
Lessons Learned from Practical Applications of BIST/B-S Technology.
Asian Test Symposium 1996: 251-257 |
| 1992 |
|---|
| 7 | | Najmi T. Jarwala,
Paul Stiling,
Enn Tammaru,
Chi W. Yau:
A Framework for Boundary-Scan Based System Test Diagnosis.
ITC 1992: 993-998 |
| 1991 |
|---|
| 6 | | Najmi T. Jarwala,
Chi W. Yau:
Achieving Board-Level BIST Using the Boundary-Scan Master.
ITC 1991: 649-658 |
| 1989 |
|---|
| 5 | | Anton T. Dahbura,
M. Ümit Uyar,
Chi W. Yau:
An Optimal Test Sequence for the JTAG/IEEE P1149.1 Test Access Port Controller.
ITC 1989: 55-62 |
| 4 | | Najmi T. Jarwala,
Chi W. Yau:
A New Framework for Analyzing Test Generation and Diagnosis Algorithms for Wiring Interconnects.
ITC 1989: 63-70 |
| 3 | | Najmi T. Jarwala,
Chi W. Yau:
A Unified Theory for Designing Optimal Test Generation and Diagnosis Algorithms for Board Interconnects.
ITC 1989: 71-77 |
| 1988 |
|---|
| 2 | | Chi W. Yau,
Song-Lin Chang,
Bruce F. Jordan,
Joe J. Schwermann,
Joan A. Wellman:
Trouble-Shooting: A Key to Process Improvement.
ITC 1988: 796-803 |
| 1986 |
|---|
| 1 | | Chi W. Yau:
Concurrent Test Generation Using AI Techniques.
ITC 1986: 722-731 |
