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| 1998 | ||
|---|---|---|
| 5 | EE | E. Kofi Vida-Torku, George Joos: Designing for scan test of high performance embedded memories. ITC 1998: 101- |
| 1994 | ||
| 4 | Craig Hunter, E. Kofi Vida-Torku, Johnny LeBlanc: Balancing Structured and Ad-hoc Design for Test: Testing of the PowerPC 603TM Microprocessor. ITC 1994: 76-83 | |
| 1992 | ||
| 3 | E. Kofi Vida-Torku: Impact of Boundary Scan Design on Delay Test. ITC 1992: 96-105 | |
| 1986 | ||
| 2 | E. Kofi Vida-Torku, James A. Monzel, Charles E. Radke: Performance Assurance of Memories Embedded in VLSI Chips. ITC 1986: 154-160 | |
| 1982 | ||
| 1 | C. C. Beh, K. H. Arya, Charles E. Radke, E. Kofi Vida-Torku: Do Stuck Fault Models Reflect Manufacturing Defects? ITC 1982: 35-42 | |
| 1 | K. H. Arya | [1] |
| 2 | C. C. Beh | [1] |
| 3 | Craig Hunter | [4] |
| 4 | George Joos | [5] |
| 5 | Johnny LeBlanc | [4] |
| 6 | James A. Monzel | [2] |
| 7 | Charles E. Radke | [1] [2] |