| |
| 2004 | ||
|---|---|---|
| 6 | EE | Wei-Lun Wang: March Based Memory Core Test Scheduling for SOC. Asian Test Symposium 2004: 248-253 |
| 2002 | ||
| 5 | EE | Wei-Lun Wang, Kuen-Jong Lee: An Efficient Deterministic Test Pattern Generator for Scan-Based BIST Environment. J. Electronic Testing 18(1): 43-53 (2002) |
| 2001 | ||
| 4 | EE | Wei-Lun Wang, Kuen-Jong Lee, Jhing-Fa Wang: An on-chip march pattern generator for testing embedded memory cores. IEEE Trans. VLSI Syst. 9(5): 730-735 (2001) |
| 2000 | ||
| 3 | EE | Wei-Lun Wang, Kuen-Jong Lee: Accelerated test pattern generators for mixed-mode BIST environments. Asian Test Symposium 2000: 368-373 |
| 1998 | ||
| 2 | EE | Kuen-Jong Lee, Wei-Lun Wang, Jhing-Fa Wang: A General Structure of Feedback Shift Registers for Built-In Self Test. J. Inf. Sci. Eng. 14(3): 645-667 (1998) |
| 1992 | ||
| 1 | Wei-Lun Wang, Jhing-Fa Wang, Kuen-Jong Lee: A Fast Testing Method for Sequential Circuits at the State Trasition Level. ITC 1992: 514-519 | |
| 1 | Kuen-Jong Lee | [1] [2] [3] [4] [5] |
| 2 | Jhing-Fa Wang | [1] [2] [4] |