Indira Nair

2008
10	EE	Reinaldo A. Bergamaschi, Guoling Han, Alper Buyuktosunoglu, Hiren D. Patel, Indira Nair, Gero Dittmann, Geert Janssen, Nagu R. Dhanwada, Zhigang Hu, Pradip Bose, John A. Darringer: Exploring power management in multi-core systems. ASP-DAC 2008: 708-713
2007
9	EE	Reinaldo A. Bergamaschi, Indira Nair, Gero Dittmann, Hiren D. Patel, Geert Janssen, Nagu R. Dhanwada, Alper Buyuktosunoglu, Emrah Acar, Gi-Joon Nam, Dorothy Kucar, Pradip Bose, John A. Darringer, Guoling Han: Performance modeling for early analysis of multi-core systems. CODES+ISSS 2007: 209-214
2004
8	EE	Valentina Salapura, Christos J. Georgiou, Indira Nair: An efficient system-on-a-chip design methodology for networking applications. CASES 2004: 212-219
2003
7	EE	Reinaldo A. Bergamaschi, Youngsoo Shin, Nagu R. Dhanwada, Subhrajit Bhattacharya, William E. Dougherty, Indira Nair, John A. Darringer, Sarala Paliwal: SEAS: a system for early analysis of SoCs. CODES+ISSS 2003: 150-155
2002
6	EE	John A. Darringer, Reinaldo A. Bergamaschi, Subhrajit Bhattacharya, Daniel Brand, Andreas Herkersdorf, Joseph K. Morrell, Indira Nair, Patricia Sagmeister, Youngsoo Shin: Early analysis tools for system-on-a-chip design. IBM Journal of Research and Development 46(6): 691-708 (2002)
1997
5	EE	Reinaldo A. Bergamaschi, Salil Raje, Indira Nair, Louise Trevillyan: Control-flow versus data-flow-based scheduling: combining both approaches in an adaptive scheduling system. IEEE Trans. VLSI Syst. 5(1): 82-100 (1997)
1995
4	EE	Ashok K. Chandra, Vijay S. Iyengar, D. Jameson, R. V. Jawalekar, Indira Nair, Barry K. Rosen, Michael P. Mullen, J. Yoon, R. Armoni, Daniel Geist, Yaron Wolfsthal: AVPGEN-A test generator for architecture verification. IEEE Trans. VLSI Syst. 3(2): 188-200 (1995)
1994
3		Ashok K. Chandra, Vijay S. Iyengar, R. V. Jawalekar, Michael P. Mullen, Indira Nair, Barry K. Rosen: Architectural Verification of Processors Using Symbolic Instruction Graphs. ICCD 1994: 454-459
1992
2		Sandip Kundu, Leendert M. Huisman, Indira Nair, Vijay S. Iyengar, Lakshmi N. Reddy: A Small Test Generator for Large Designs. ITC 1992: 30-40
1986
1		Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman: Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529

Coauthor Index

1	Emrah Acar	[9]
2	R. Armoni	[4]
3	Zeev Barzilai	[1]
4	Reinaldo A. Bergamaschi	[5] [6] [7] [9] [10]
5	Subhrajit Bhattacharya	[6] [7]
6	Pradip Bose	[9] [10]
7	Daniel Brand	[6]
8	Alper Buyuktosunoglu	[9] [10]
9	J. Lawrence Carter	[1]
10	Ashok K. Chandra	[3] [4]
11	John A. Darringer	[6] [7] [9] [10]
12	Nagu R. Dhanwada	[7] [9] [10]
13	Gero Dittmann	[9] [10]
14	William E. Dougherty	[7]
15	Daniel Geist	[4]
16	Christos J. Georgiou	[8]
17	Guoling Han	[9] [10]
18	Andreas Herkersdorf	[6]
19	Zhigang Hu	[10]
20	Leendert M. Huisman	[2]
21	Vijay S. Iyengar	[1] [2] [3] [4]
22	D. Jameson	[4]
23	Geert Janssen	[9] [10]
24	R. V. Jawalekar	[3] [4]
25	Dorothy Kucar	[9]
26	Sandip Kundu	[2]
27	Joseph K. Morrell	[6]
28	Michael P. Mullen	[3] [4]
29	Gi-Joon Nam	[9]
30	Sarala Paliwal	[7]
31	Hiren D. Patel	[9] [10]
32	Salil Raje	[5]
33	Lakshmi N. Reddy	[2]
34	Barry K. Rosen	[1] [3] [4]
35	Joe D. Rutledge	[1]
36	Patricia Sagmeister	[6]
37	Valentina Salapura	[8]
38	Youngsoo Shin	[6] [7]
39	Gabriel M. Silberman	[1]
40	Louise Trevillyan	[5]
41	Yaron Wolfsthal (Yaron Wolfstahl)	[4]
42	J. Yoon	[4]