| 1996 |
|---|
| 11 | EE | Jaushin Lee,
Janak H. Patel:
Hierarchical test generation under architectural level functional constraints.
IEEE Trans. on CAD of Integrated Circuits and Systems 15(9): 1144-1151 (1996) |
| 1994 |
|---|
| 10 | EE | Jaushin Lee,
Janak H. Patel:
Architectural level test generation for microprocessors.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(10): 1288-1300 (1994) |
| 9 | EE | Vivek Chickermane,
Jaushin Lee,
Janak H. Patel:
Addressing design for testability at the architectural level.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(7): 920-934 (1994) |
| 1993 |
|---|
| 8 | EE | Jaushin Lee,
Janak H. Patel:
An architectural level test generator based on nonlinear equation solving.
J. Electronic Testing 4(2): 137-150 (1993) |
| 1992 |
|---|
| 7 | EE | Jaushin Lee,
Janak H. Patel:
Hierarchical Test Generation under Intensive Global Functional Constraints.
DAC 1992: 261-266 |
| 6 | EE | Vivek Chickermane,
Jaushin Lee,
Janak H. Patel:
A comparative study of design for testability methods using high-level and gate-level descriptions.
ICCAD 1992: 620-624 |
| 5 | | Jaushin Lee,
Janak H. Patel:
An Instruction Sequence Assembling Methodology for Testing Microprocessors.
ITC 1992: 49-58 |
| 4 | | Vivek Chickermane,
Jaushin Lee,
Janak H. Patel:
Design for Testability Using Architectural Descriptions.
ITC 1992: 752-761 |
| 1991 |
|---|
| 3 | | Jaushin Lee,
Janak H. Patel:
An Architectural Level Test Generator for a Hierarchical Design Environment.
FTCS 1991: 44-51 |
| 2 | | Jaushin Lee,
Janak H. Patel:
A Signal-Driven Discrete Relaxation Technique for Architectural Level Test Generation.
ICCAD 1991: 458-461 |
| 1 | | Jaushin Lee,
Janak H. Patel:
ARTEST: An Architectural Level Test Generator for Data Path Faults and Control Faults.
ITC 1991: 729-738 |
