2008 |
24 | EE | Chung-Chi Lin,
Ming-Hwa Sheu,
Huann-Keng Chiang,
Chishyan Liaw,
Zeng-chuan Wu:
The efficient VLSI design of BI-CUBIC convolution interpolation for digital image processing.
ISCAS 2008: 480-483 |
23 | EE | Jin-Fa Lin,
Yin-Tsung Hwang,
Ming-Hwa Sheu:
Low Complexity Dual-Mode Pulse Generator Designs.
IEICE Transactions 91-A(7): 1812-1815 (2008) |
22 | EE | Su-Hon Lin,
Ming-Hwa Sheu:
Area-Time Efficient Modulo 2n - 1 Adder Design Using Hybrid Carry Selection.
IEICE Transactions 91-D(2): 361-362 (2008) |
21 | EE | Su-Hon Lin,
Ming-Hwa Sheu,
Chao-Hsiang Wang:
Efficient VLSI Design of Residue-to-Binary Converter for the Moduli Set (2n, 2n+1 - 1, 2n - 1).
IEICE Transactions 91-D(7): 2058-2060 (2008) |
2007 |
20 | EE | Shyue-Wen Yang,
Ming-Hwa Sheu,
Chun-Kai Yeh,
Chih-Yuen Wen,
Chih-Chieh Lin,
Wen-Kai Tsai:
Fast Fair Crossbar Scheduler for On-chip Router.
ISCAS 2007: 385-388 |
19 | EE | Chung-Chi Lin,
Ming-Hwa Sheu,
Huann-Keng Chiang,
Chih-Jen Wei,
Chishyan Liaw:
A High-Performance Architecture of Motion Adaptive De-interlacing with Reliable Interfield Information.
IEICE Transactions 90-A(11): 2575-2583 (2007) |
2006 |
18 | EE | Chung-Chi Lin,
Ming-Hwa Sheu,
Huann-Keng Chiang,
Chih-Jen Wei:
The VLSI Design of Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection.
APCCAS 2006: 1587-1590 |
17 | EE | Su-Hon Lin,
Ming-Hwa Sheu,
Jing-Shiun Lin,
Wen-Tsai Sheu:
Efficient VLSI Design for RNS Reverse Converter Based on New Moduli Set (2n-1, 2n+1, 22n+1).
APCCAS 2006: 2020-2023 |
16 | EE | Yin-Tsung Hwang,
Jin-Fa Lin,
Ming-Hwa Sheu,
Chia-Jen Sheu:
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.
APCCAS 2006: 594-597 |
15 | EE | Chung-Chi Lin,
Ming-Hwa Sheu,
Huann-Keng Chiang,
Chishyan Liaw,
Ming-che Chen:
Film-to-Video Conversion with Scene Cut Detection.
ICICIC (1) 2006: 285-289 |
14 | EE | Jin-Fa Lin,
Yin-Tsung Hwang,
Ming-Hwa Sheu,
Cheng-Che Ho:
A high speed and energy efficient full adder design using complementary & level restoring carry logic.
ISCAS 2006 |
13 | EE | Chung-Chi Lin,
Chih-Jen Wei,
Ming-Hwa Sheu,
Huann-Keng Chiang,
Chishyan Liaw:
The VLSI design of de-interlacing with scene change detection.
ISCAS 2006 |
2005 |
12 | EE | Shyue-Wen Yang,
Ming-Hwa Sheu,
Hsien-Huang P. Wu,
Hung-En Chien,
Ping-Kuo Weng,
Ying-Yih Wu:
VLSI architecture design for a fast parallel label assignment in binary image.
ISCAS (3) 2005: 2393-2396 |
11 | EE | Hsien-Huang P. Wu,
Ming-Hwa Sheu,
Tung-Yu Yang:
Directional interpolation for field-sequential stereoscopic video.
ISCAS (3) 2005: 2879-2882 |
10 | EE | Chung-Chi Lin,
Ming-Hwa Sheu,
Huann-Keng Chiang,
Chishyan Liaw:
Motion Adaptive De-interlacing with Horizontal and Vertical Motions Detection.
PCM (1) 2005: 291-302 |
2003 |
9 | EE | Chichyang Chen,
Rui-Lin Chen,
Ming-Hwa Sheu:
A Fast Additive Normalization Method for Exponential Computation.
DSD 2003: 286-293 |
2002 |
8 | EE | Ming-Hwa Sheu,
Su-Hon Lin:
Fast design approach for implementing the approximate squaring function.
APCCAS (2) 2002: 25-29 |
2001 |
7 | EE | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders.
ISCAS (4) 2001: 206-209 |
6 | EE | Ming-Hwa Sheu,
Ho En Liao,
Shih Tsung Kan,
Ming-Der Shieh:
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter.
ISCAS (4) 2001: 446-449 |
5 | EE | Ming-Der Shieh,
Ming-Hwa Sheu,
Chung-Ho Chen,
Hsin-Fu Lo:
A Systematic Approach for Parallel CRC Computations.
J. Inf. Sci. Eng. 17(3): 445-461 (2001) |
2000 |
4 | EE | Ming-Der Shieh,
Hsin-Fu Lo,
Ming-Hwa Sheu:
High-speed generation of LFSR signatures.
Asian Test Symposium 2000: 222- |
1999 |
3 | EE | Che-Han Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Ming-Hwa Sheu,
Jia-Lin Sheu:
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.
ISCAS (1) 1999: 500-503 |
1993 |
2 | | Ming-Hwa Sheu,
Jhing-Fa Wang,
Jau-Yien Lee,
Lian-Ying Liu:
An Expandable Chip Desing for Gray-scale Morphological Operations.
ISCAS 1993: 1563-1566 |
1 | | Ming-Hwa Sheu,
Jau-Yien Lee,
Jhing-Fa Wang,
An-Nan Suen,
Lian-Ying Liu:
A High Throughput-Rate Architecture for 8*8 2-D DCT.
ISCAS 1993: 1578-1590 |