Hideo Ito

2009
44	EE	Kazuteru Namba, Yoshikazu Matsui, Hideo Ito: Test Compression for IP Core Testing with Reconfigurable Network and Fixing-Flipping Coding. J. Electronic Testing 25(1): 97-105 (2009)
2008
43	EE	Shuangyu Ruan, Kazuteru Namba, Hideo Ito: Soft Error Hardened FF Capable of Detecting Wide Error Pulse. DFT 2008: 272-280
42	EE	Kazuteru Namba, Hideo Ito: Delay Fault Testability on Two-Rail Logic Circuits. DFT 2008: 482-490
41	EE	Masato Kitakami, Bochuan Cai, Hideo Ito: A Checkpointing Method with Small Checkpoint Latency. IEICE Transactions 91-D(3): 857-861 (2008)
40	EE	Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Circuit and Latch Capable of Masking Soft Errors with Schmitt Trigger. J. Electronic Testing 24(1-3): 11-19 (2008)
39	EE	Toshinori Takabatake, Tomoki Nakamigawa, Hideo Ito: Connectivity of Generalized Hierarchical Completely-Connected Networks. Journal of Interconnection Networks 9(1/2): 127-139 (2008)
2007
38	EE	Takashi Ikeda, Kazuteru Namba, Hideo Ito: Soft Error Hardened Latch Scheme for Enhanced Scan Based Delay Fault Testing. DFT 2007: 282-290
37	EE	Abderrahim Doumar, Kentaroh Katoh, Hideo Ito: Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability. DFT 2007: 31-40
36	EE	Gang Zeng, Hideo Ito: Low-Cost IP Core Test Using Tri-Template-Based Codes. IEICE Transactions 90-D(1): 288-295 (2007)
2006
35	EE	Gang Zeng, Hideo Ito: Concurrent core test for SOC using shared test set and scan chain disable. DATE 2006: 1045-1050
34	EE	Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito: Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. DFT 2006: 136-144
33	EE	Yoichi Sasaki, Kazuteru Namba, Hideo Ito: Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. DFT 2006: 327-335
32	EE	Kentaroh Katoh, Hideo Ito: Built-In Self-Test for PEs of Coarse Grained Dynamically Reconfigurable Devices. European Test Symposium 2006: 69-74
31	EE	Gang Zeng, Hideo Ito: Concurrent Core Testing for SOC Using Merged Test Set and Scan Tree. IEICE Transactions 89-D(3): 1157-1164 (2006)
30	EE	Kazuteru Namba, Hideo Ito: Proposal of Testable Multi-Context FPGA Architecture. IEICE Transactions 89-D(5): 1687-1693 (2006)
29	EE	Kazuteru Namba, Hideo Ito: Redundant Design for Wallace Multiplier. IEICE Transactions 89-D(9): 2512-2524 (2006)
2005
28	EE	Gang Zeng, Hideo Ito: Concurrent Core Test for Test Cost Reduction Using Merged Test Set and Scan Tree. ICCD 2005: 143-146
27	EE	Kentaroh Katoh, Abderrahim Doumar, Hideo Ito: Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift. IOLTS 2005: 203-204
26	EE	Kazuteru Namba, Hideo Ito: Design of Defect Tolerant Wallace Multiplier. PRDC 2005: 300-304
25	EE	Kazuteru Namba, Hideo Ito: Scan Design for Two-Pattern Test without Extra Latches. IEICE Transactions 88-D(12): 2777-2785 (2005)
24	EE	Gang Zeng, Hideo Ito: Hybrid Pattern BIST for Low-Cost Core Testing Using Embedded FPGA Core. IEICE Transactions 88-D(5): 984-992 (2005)
23	EE	Gang Zeng, Hideo Ito: X-Tolerant Test Data Compression for SOC with Enhanced Diagnosis Capability. IEICE Transactions 88-D(7): 1662-1670 (2005)
22	EE	Kazuteru Namba, Hideo Ito: Deterministic Delay Fault BIST Using Adjacency Test Pattern Generation. IEICE Transactions 88-D(9): 2135-2142 (2005)
2004
21	EE	Gang Zeng, Hideo Ito: Non-Intrusive Test Compression for SOC Using Embedded FPGA Core. DFT 2004: 413-421
20	EE	Manabu Sueishi, Masato Kitakami, Hideo Ito: Fault-Tolerant Message Switching Based on Wormhole Switching and Backtracking. PRDC 2004: 183-190
19	EE	Gang Zeng, Hideo Ito: Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core. VTS 2004: 355-360
2003
18	EE	Gang Zeng, Hideo Ito: Efficient Test Data Decompression for System-on-a-Chip Using an Embedded FPGA Core. DFT 2003: 503-510
17	EE	Abderrahim Doumar, Hideo Ito: Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey. IEEE Trans. VLSI Syst. 11(3): 386-405 (2003)
2002
16	EE	Lihong Tong, Kazuki Suzuki, Hideo Ito: Optimal Seed Generation for Delay Fault Detection BIST. Asian Test Symposium 2002: 116-121
15		Toshinori Takabatake, Masato Kitakami, Hideo Ito: A Fault-tolerant Routing Strategy for Generalized Hierarchical Completely-connected Networks. IASTED PDCS 2002: 619-624
14	EE	Toshinori Takabatake, Masato Kitakami, Hideo Ito: Fault-Tolerant Properties of Generalized Hierarchical Completely-Connected Networks. PRDC 2002: 137-144
2001
13	EE	Toshinori Takabatake, Masato Kitakami, Hideo Ito: Escape and Restoration Routing: Suspensive Deadlock Recovery in Interconnection Networks. PRDC 2001: 127-136
12	EE	Masato Kitakami, Shunji Kubota, Hideo Ito: Fault-Tolerance of Functional Programs Based on the Parallel Graph Reduction. PRDC 2001: 319-324
2000
11	EE	Abderrahim Doumar, Hideo Ito: Testing approach within FPGA-based fault tolerant systems. Asian Test Symposium 2000: 411-416
10	EE	Abderrahim Doumar, Hideo Ito: Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources. DFT 2000: 134-142
1999
9	EE	Abderrahim Doumar, Hideo Ito: Testing the Logic Cells and Interconnect Resources for FPGAs. Asian Test Symposium 1999: 369-374
8	EE	Abderrahim Doumar, Satoshi Kaneko, Hideo Ito: Defect and Fault Tolerance FPGAs by Shifting the Configuration Data. DFT 1999: 377-385
7	EE	Keiichi Kaneko, Hideo Ito: Fault-Tolerant Routing Algorithms for Hypercube Networks. IPPS/SPDP 1999: 218-224
6	EE	Toshinori Takabatake, Keiichi Kaneko, Hideo Ito: Generalized Hierarchical Completely-Connected Networks. ISPAN 1999: 68-73
5	EE	Mikio Yagi, Keiichi Kaneko, Hideo Ito: LLT and LTn Schemes: Error Recovery Schemes in Mobile Environments. PRDC 1999: 23-
4	EE	Abderrahim Doumar, Hideo Ito: An Automatic Testing and Diagnosis for FPGAs. PRDC 1999: 45-
1998
3	EE	Hammadi Nait-Charif, Hideo Ito: Improving the Performance of Feedforward Neural Networks by Noise Injection into Hidden Neurons. Journal of Intelligent and Robotic Systems 21(2): 103-115 (1998)
1994
2		Hideo Ito, Takashi Yagi: Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. DFT 1994: 177-184
1993
1		Hideo Ito: A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. DFT 1993: 80-87

Coauthor Index

1	Bochuan Cai	[41]
2	Abderrahim Doumar	[4] [8] [9] [10] [11] [17] [27] [37]
3	Takashi Ikeda	[38]
4	Keiichi Kaneko	[5] [6] [7]
5	Satoshi Kaneko	[8]
6	Kentaroh Katoh	[27] [32] [37]
7	Masato Kitakami	[12] [13] [14] [15] [20] [41]
8	Shunji Kubota	[12]
9	Yoshikazu Matsui	[44]
10	Hammadi Nait-Charif	[3]
11	Tomoki Nakamigawa	[39]
12	Kazuteru Namba	[22] [25] [26] [29] [30] [33] [38] [40] [42] [43] [44]
13	Shuangyu Ruan	[43]
14	Yoichi Sasaki	[33] [40]
15	Youhua Shi	[34]
16	Manabu Sueishi	[20]
17	Kazuki Suzuki	[16]
18	Toshinori Takabatake	[6] [13] [14] [15] [34] [39]
19	Lihong Tong	[16]
20	Mikio Yagi	[5]
21	Takashi Yagi	[2]
22	Masao Yanagisawa	[34]
23	Gang Zeng	[18] [19] [21] [23] [24] [28] [31] [34] [35] [36]

Colors in the list of coauthors