2009 |
15 | EE | Chih-Da Chien,
Cheng-An Chien,
Jui-Chin Chu,
Jiun-In Guo,
Ching-Hwa Cheng:
A 252Kgates/4.9Kbytes SRAM/71mW multistandard video decoder for high definition video applications.
ACM Trans. Design Autom. Electr. Syst. 14(1): (2009) |
2008 |
14 | EE | Ming-Chien Tsai,
Ching-Hwa Cheng,
Chiou-Mao Yang:
An All-Digital High-Precision Built-In Delay Time Measurement Circuit.
VTS 2008: 249-254 |
2007 |
13 | EE | Chang-Tzu Lin,
Tai-Wei Kung,
De-Sheng Chen,
Yi-Wen Wang,
Ching-Hwa Cheng:
Noise-Aware Floorplanning for Fast Power Supply Network Design.
ISCAS 2007: 2028-2031 |
12 | EE | Hsiang-Hui Huang,
Ching-Hwa Cheng:
Using Clock-Vdd to Test and Diagnose the Power-Switch in Power-Gating Circuit.
VTS 2007: 110-118 |
2003 |
11 | EE | Ching-Hwa Cheng:
Design Scan Test Strategy for Single Phase Dynamic Circuits.
DFT 2003: 199- |
2002 |
10 | EE | Ching-Hwa Cheng:
Adaptable Voltage Scan Testing of Charge-Sharing Faults for Domino Circuits.
DFT 2002: 147-158 |
2001 |
9 | EE | Shih-Chieh Chang,
Ching-Hwa Cheng,
Wen-Ben Jone,
Shin-De Lee,
Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001) |
2000 |
8 | EE | Yin-He Su,
Ching-Hwa Cheng,
Shih-Chieh Chang:
Novel techniques for improving testability analysis.
Asian Test Symposium 2000: 392-397 |
7 | EE | Ching-Hwa Cheng,
Wen-Ben Jone,
Jinn-Shyan Wang,
Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits.
Asian Test Symposium 2000: 435-440 |
6 | EE | Ching-Hwa Cheng,
Jinn-Shyan Wang,
Shih-Chieh Chang,
Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
DFT 2000: 329-337 |
5 | | Ching-Hwa Cheng,
Shih-Chieh Chang,
Shin-De Li,
Wen-Ben Jone,
Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
ICCAD 2000: 387-390 |
1999 |
4 | EE | Ching-Hwa Cheng,
Shih-Chieh Chang,
Jinn-Shyan Wang,
Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits.
DFT 1999: 77-85 |
1997 |
3 | | Yung-Yuan Chen,
Shambhu J. Upadhyaya,
Ching-Hwa Cheng:
A Comprehensive Reconfiguration Scheme for Fault-Tolerant VLSI/WSI Array Processors.
IEEE Trans. Computers 46(12): 1363-1371 (1997) |
1995 |
2 | EE | Yung-Yuan Chen,
Ching-Hwa Cheng,
Jwu-E Chen:
An efficient switching network fault diagnosis for reconfigurable VLSI/WSI array processors.
VLSI Design 1995: 349-354 |
1994 |
1 | | Yung-Yuan Chen,
Ching-Hwa Cheng,
Yung-Ci Chou:
An Effective Reconfiguration Process for Fault-Tolerant VLSI/WSI Array Processors.
EDCC 1994: 421-438 |