| 2007 |
|---|
| 8 | EE | Abderrahim Doumar,
Kentaroh Katoh,
Hideo Ito:
Fault Tolerant SoC Architecture Design for JPEG2000 Using Partial Reconfigurability.
DFT 2007: 31-40 |
| 2005 |
|---|
| 7 | EE | Kentaroh Katoh,
Abderrahim Doumar,
Hideo Ito:
Design of On-Line Testing for SoC with IEEE P1500 Compliant Cores Using Reconfigurable Hardware and Scan Shift.
IOLTS 2005: 203-204 |
| 2003 |
|---|
| 6 | EE | Abderrahim Doumar,
Hideo Ito:
Detecting, diagnosing, and tolerating faults in SRAM-based field programmable gate arrays: a survey.
IEEE Trans. VLSI Syst. 11(3): 386-405 (2003) |
| 2000 |
|---|
| 5 | EE | Abderrahim Doumar,
Hideo Ito:
Testing approach within FPGA-based fault tolerant systems.
Asian Test Symposium 2000: 411-416 |
| 4 | EE | Abderrahim Doumar,
Hideo Ito:
Design of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources.
DFT 2000: 134-142 |
| 1999 |
|---|
| 3 | EE | Abderrahim Doumar,
Hideo Ito:
Testing the Logic Cells and Interconnect Resources for FPGAs.
Asian Test Symposium 1999: 369-374 |
| 2 | EE | Abderrahim Doumar,
Satoshi Kaneko,
Hideo Ito:
Defect and Fault Tolerance FPGAs by Shifting the Configuration Data.
DFT 1999: 377-385 |
| 1 | EE | Abderrahim Doumar,
Hideo Ito:
An Automatic Testing and Diagnosis for FPGAs.
PRDC 1999: 45- |
