| 2008 |
|---|
| 38 | EE | Tzu-Yuan Kuo,
Jinn-Shyan Wang:
A low-voltage latch-adder based tree multiplier.
ISCAS 2008: 804-807 |
| 2006 |
|---|
| 37 | EE | Chingwei Yeh,
Chao-Ching Wang,
Lin-Chi Lee,
Jinn-Shyan Wang:
A 124.8Msps, 15.6mW field-programmable variable-length codec for multimedia applications.
DATE Designers' Forum 2006: 239-243 |
| 36 | EE | Chingwei Yeh,
En-Feng Hsu,
Kai-Wen Cheng,
Jinn-Shyan Wang,
Nai-Jen Chang:
An 830mW, 586kbps 1024-bit RSA chip design.
DATE Designers' Forum 2006: 24-29 |
| 35 | EE | Jia-Wei Chen,
Chun-Hao Chang,
Chien-Chang Lin,
Yi-Huan Yang,
Jiun-In Guo,
Jinn-Shyan Wang:
A Condition-based Intra Prediction Algorithm for H.264/AVC.
ICME 2006: 1077-1080 |
| 34 | EE | Jia-Wei Chen,
Kuan-Hung Chen,
Jinn-Shyan Wang,
Jiun-In Guo:
A performance-aware IP core design for multimode transform coding using scalable-DA algorithm.
ISCAS 2006 |
| 33 | EE | Jinn-Shyan Wang,
Yi-Ming Wang,
Chun-Yuan Cheng,
Yu-Chai Liu:
An improved SAR controller for DLL applications.
ISCAS 2006 |
| 32 | EE | Jinn-Shyan Wang,
Yu-Juey Chang,
Chingwei Yeh,
Yuan-Hua Chu:
Design of STR level converters for SoCs using the multi-island dual-VDD design technique.
ISCAS 2006 |
| 31 | EE | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang:
A high-performance direct 2-D transform coding IP design for MPEG-4AVC/H.264.
IEEE Trans. Circuits Syst. Video Techn. 16(4): 472-483 (2006) |
| 2005 |
|---|
| 30 | EE | Yi-Ming Wang,
Chang-Fen Hu,
Yi-Jen Chen,
Jinn-Shyan Wang:
An all-digital pulsewidth control loop.
ISCAS (2) 2005: 1258-1261 |
| 29 | EE | Jinn-Shyan Wang,
Shiang-Jiun Lin,
Chingwei Yeh:
A low-power high-SFDR CMOS direct digital frequency synthesizer.
ISCAS (2) 2005: 1670-1673 |
| 28 | EE | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang:
An efficient direct 2-D transform coding IP design for MPEG-4 AVC/H.264.
ISCAS (5) 2005: 4517-4520 |
| 27 | EE | Kuan-Hung Chen,
Kuo-Chuan Chao,
Jinn-Shyan Wang,
Yuan-Sun Chu,
Jiun-In Guo:
An efficient spurious power suppression technique (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design.
ISLPED 2005: 155-160 |
| 26 | EE | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh,
Jia-Wei Chen:
An Energy-Aware IP Core Design for the Variable-Length DCT/IDCT Targeting at MPEG4 Shape-Adaptive Transforms.
IEEE Trans. Circuits Syst. Video Techn. 15(5): 704-715 (2005) |
| 2004 |
|---|
| 25 | EE | Yi-Ming Wang,
Jinn-Shyan Wang:
A reliable low-power fast skew-compensation circuit.
ASP-DAC 2004: 547-548 |
| 24 | | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh:
A power-aware SNR-progressive DCT/IDCT IP core design for multimedia transform coding.
ICME 2004: 1683-1686 |
| 23 | | Kuan-Hung Chen,
Jiun-In Guo,
Jinn-Shyan Wang,
Ching-Wei Yeh,
Tien-Fu Chen:
A power-aware IP core design for the variable-length DCT/IDCT targeting at MPEG4 shape-adaptive transforms.
ISCAS (2) 2004: 141-144 |
| 22 | | Jinn-Shyan Wang,
Shang-Jyh Shieh,
Ching-Wei Yeh,
Yuan-Hsun Yeh:
Pseudo-footless CMOS domino logic circuits for high-performance VLSI designs.
ISCAS (2) 2004: 401-404 |
| 21 | | Yi-Ming Wang,
Jinn-Shyan Wang:
An all-digital 50% duty-cycle corrector.
ISCAS (2) 2004: 925-928 |
| 20 | EE | Jinn-Shyan Wang,
Chien-Nan Kuo,
Tsung-Han Yang:
Low-power fixed-width array multipliers.
ISLPED 2004: 307-312 |
| 2003 |
|---|
| 19 | EE | Wen-Ben Jone,
Jinn-Shyan Wang,
Hsueh-I Lu,
I. P. Hsu,
J.-Y. Chen:
Design theory and implementation for low-power segmented bus systems.
ACM Trans. Design Autom. Electr. Syst. 8(1): 38-54 (2003) |
| 18 | EE | Hung-Cheng Wu,
Tien-Fu Chen,
Hung-Yu Li,
Jinn-Shyan Wang:
Energy Efficient Caching-on-Cache Architectures for Embedded Systems.
J. Inf. Sci. Eng. 19(5): 809-825 (2003) |
| 2002 |
|---|
| 17 | EE | Yuan-Pao Hsu,
Kao-Shing Hwang,
Jinn-Shyan Wang:
An Associative Architecture of CMAC for Mobile Robot Motion Control.
J. Inf. Sci. Eng. 18(2): 145-161 (2002) |
| 2001 |
|---|
| 16 | EE | Sheng-Yeh Lai,
Jinn-Shyan Wang:
A high-efficiency CMOS charge pump circuit.
ISCAS (4) 2001: 406-409 |
| 15 | EE | Chung-Hsun Huang,
Jinn-Shyan Wang,
Yan-Chao Huang:
A high-speed CMOS incrementer/decrementer.
ISCAS (4) 2001: 88-91 |
| 14 | EE | Shih-Chieh Chang,
Ching-Hwa Cheng,
Wen-Ben Jone,
Shin-De Lee,
Jinn-Shyan Wang:
Charge-sharing alleviation and detection for CMOS domino circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 20(2): 266-280 (2001) |
| 2000 |
|---|
| 13 | EE | Jinn-Shyan Wang,
Po-Hui Yang:
Power analysis and implementation of a low-power 300 MHz 8-b × 8-b pipelined multiplier.
ASP-DAC 2000: 225-228 |
| 12 | EE | Yuan-Bao Hsu,
Kao-Shing Hwang,
Chien-Yuan Pao,
Jinn-Shyan Wang:
A new CMAC neural network architecture and its ASIC realization.
ASP-DAC 2000: 481-484 |
| 11 | EE | Ching-Hwa Cheng,
Wen-Ben Jone,
Jinn-Shyan Wang,
Shih-Chieh Chang:
Charge sharing fault analysis and testing for CMOS domino logic circuits.
Asian Test Symposium 2000: 435-440 |
| 10 | EE | Ching-Hwa Cheng,
Jinn-Shyan Wang,
Shih-Chieh Chang,
Wen-Ben Jone:
Low-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.
DFT 2000: 329-337 |
| 9 | | Ching-Hwa Cheng,
Shih-Chieh Chang,
Shin-De Li,
Wen-Ben Jone,
Jinn-Shyan Wang:
Synthesis of CMOS Domino Circuits for Charge Sharing Alleviation.
ICCAD 2000: 387-390 |
| 1999 |
|---|
| 8 | EE | Ching-Wei Yeh,
Chin-Chao Chang,
Jinn-Shyan Wang:
Technnology Mapping for Low Power.
ASP-DAC 1999: 145-148 |
| 7 | EE | Ching-Wei Yeh,
Yin-Shuin Kang,
Shan-Jih Shieh,
Jinn-Shyan Wang:
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs.
DAC 1999: 62-67 |
| 6 | EE | Ching-Hwa Cheng,
Shih-Chieh Chang,
Jinn-Shyan Wang,
Wen-Ben Jone:
Charge Sharing Fault Detection for CMOS Domino Logic Circuits.
DFT 1999: 77-85 |
| 5 | EE | Ching-Rong Chang,
Jinn-Shyan Wang:
A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM.
ISCAS (1) 1999: 254-257 |
| 4 | EE | Chingwei Yeh,
Chin-Chao Chang,
Jinn-Shyan Wang:
A cell selection strategy for low power applications.
ISCAS (6) 1999: 416-419 |
| 3 | EE | J.-Y. Chen,
Wen-Ben Jone,
Jinn-Shyan Wang,
Hsueh-I Lu,
T. F. Chen:
Segmented bus design for low-power systems.
IEEE Trans. VLSI Syst. 7(1): 25-29 (1999) |
| 1998 |
|---|
| 2 | EE | Jinn-Shyan Wang,
Po-Hui Yang,
Wayne Tseng:
Low-power embedded SRAM macros with current-mode read/write operations.
ISLPED 1998: 282-287 |
| 1995 |
|---|
| 1 | | Hong-Yi Huang,
Jinn-Shyan Wang,
Yuan-Hua Chu,
Tain-Shun Wu,
Kuo-Hsing Cheng,
Chung-Yu Wu:
Low-Voltage Low-Power CMOS True-Single-Phase Clocking Scheme with Locally Asynchronous Logic Circuits.
ISCAS 1995: 1572-1575 |
