| 2002 |
|---|
| 5 | EE | Cho W. Moon,
Harish Kriplani,
Krishna P. Belkhale:
Timing model extraction of hierarchical blocks by graph reduction.
DAC 2002: 152-157 |
| 1995 |
|---|
| 4 | EE | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Pattern independent maximum current estimation in power and ground buses of CMOS VLSI circuits: Algorithms, signal correlations, and their resolution.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 998-1012 (1995) |
| 1994 |
|---|
| 3 | | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Improved Delay and Current Models for Estimating Maximum Currents in CMOS VLSI Circuits.
ISCAS 1994: 435-438 |
| 1993 |
|---|
| 2 | EE | Harish Kriplani,
Farid N. Najm,
Ping Yang,
Ibrahim N. Hajj:
Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits.
DAC 1993: 384-388 |
| 1992 |
|---|
| 1 | EE | Harish Kriplani,
Farid N. Najm,
Ibrahim N. Hajj:
Maximum Current Estimation in CMOS Circuits.
DAC 1992: 2-7 |
