| 2007 |
|---|
| 27 | | Wing Ning Li,
Thomas Schweiger:
Distributed Data Structures and Algorithms for Disjoint Sets in Computing Connected Components of Huge Network.
PDPTA 2007: 905-909 |
| 26 | EE | Craig W. Thompson,
Wing Ning Li,
Zhichun Xiao:
Workflow Planning on a Grid.
IEEE Internet Computing 11(1): 74-77 (2007) |
| 2006 |
|---|
| 25 | EE | Zhichun Xiao,
Craig W. Thompson,
Wing Ning Li:
Data Processing Workflow Automation in Grid Architecture.
GCC Workshops 2006: 189-195 |
| 24 | | Roopa Bheemavaram,
Johnson Zhang,
Wing Ning Li:
Efficient Algorithms for Grouping Data to Improve Data Quality.
IKE 2006: 149-154 |
| 2005 |
|---|
| 23 | EE | Zhichun Xiao,
Wing Ning Li,
John Jing-Fu Jenq:
On unit task linear-nonlinear two-cluster scheduling problem.
SAC 2005: 713-717 |
| 2004 |
|---|
| 22 | | John Jing-Fu Jenq,
Wing Ning Li:
Parallel Thinning on Rmesh.
Computers and Their Applications 2004: 164-167 |
| 21 | | Wing Ning Li,
Zhichun Xiao,
John Jing-Fu Jenq:
An Exact Scheduling Algorithm for Two, Linear-Nonlinear Clusters, With A Common Communication Delay.
PDPTA 2004: 1095-1101 |
| 2003 |
|---|
| 20 | EE | Wing Ning Li:
Convergent transfer subgraph characterization and computation.
ISCAS (3) 2003: 248-251 |
| 19 | | Chia-Chyi Li,
Wing Ning Li:
A Novel Computational Model for Predicting Interactive Sites of Proteins.
METMBS 2003: 72-76 |
| 18 | | Chia-Chyi Li,
Wing Ning Li:
PISMOL: A Software Tool for Protein Interactive Site Prediction Model Development.
METMBS 2003: 77-81 |
| 2000 |
|---|
| 17 | EE | Wing Ning Li,
Jing-Fu Fu Jenq:
On the Thread Scheduling Problem.
J. UCS 6(10): 994-1014 (2000) |
| 1998 |
|---|
| 16 | | Jing-Fu Fu Jenq,
Wing Ning Li:
Artificial Neural Networks on Reconfigurable Meshes.
IPPS/SPDP Workshops 1998: 234-242 |
| 15 | EE | Wing Ning Li:
Towards a hierarchical design and integration of programming projects.
SIGCSE 1998: 121-125 |
| 14 | EE | John Jing-Fu Jenq,
Wing Ning Li:
Feedforward backpropagation artificial neural networks on reconfigurable meshes.
Future Generation Comp. Syst. 14(5-6): 313-319 (1998) |
| 1997 |
|---|
| 13 | EE | Wing Ning Li:
Two-segmented Channel Routing Is Strong NP-complete.
Discrete Applied Mathematics 78(1-3): 291-298 (1997) |
| 1996 |
|---|
| 12 | EE | Wing Ning Li,
Ravi Kiran:
An object-oriented design and implementation of reusable graph objects with C++: a case study.
SAC 1996: 510-514 |
| 1995 |
|---|
| 11 | EE | Jing-Fu Fu Jenq,
Wing Ning Li:
Optimal hypercube algorithms for robot configuration space computation.
SAC 1995: 182-186 |
| 10 | EE | Wing Ning Li:
An efficient algorithm for computing a minimum node cutset from a vertex-disjoint path set for timing optimization.
SAC 1995: 56-60 |
| 9 | EE | Wing Ning Li:
The complexity of segmented channel routing.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 518-523 (1995) |
| 1994 |
|---|
| 8 | EE | Wing Ning Li:
On the equivalence of pull-up transistor assignment in PLA folding and distribution graph.
SAC 1994: 374-378 |
| 1993 |
|---|
| 7 | | Wing Ning Li:
Strongly NP-Hard Discrete Gate Sizing Problems.
ICCD 1993: 468-471 |
| 6 | EE | Wing Ning Li,
Andrew Lim,
Prathima Agrawal,
Sartaj Sahni:
On the circuit implementation problem.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(8): 1147-1156 (1993) |
| 1992 |
|---|
| 5 | EE | Wing Ning Li,
Andrew Lim,
Prathima Agrawal,
Sartaj Sahni:
On the Circuit Implementation Problem.
DAC 1992: 478-483 |
| 1990 |
|---|
| 4 | EE | Wing Ning Li,
Sudhakar M. Reddy,
Sartaj Sahni:
Long and short covering edges in combination logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(12): 1245-1253 (1990) |
| 3 | EE | Wing Ning Li,
Sartaj Sahni:
Pull up transistor folding.
IEEE Trans. on CAD of Integrated Circuits and Systems 9(5): 512-521 (1990) |
| 1989 |
|---|
| 2 | EE | Wing Ning Li,
Sudhakar M. Reddy,
Sartaj K. Sahni:
On path selection in combinational logic circuits.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(1): 56-63 (1989) |
| 1988 |
|---|
| 1 | EE | Wing Ning Li,
Sudhakar M. Reddy,
Sartaj Sahni:
On Path Selection in Combinational Logic Circuits.
DAC 1988: 142-147 |
