| 2002 |
|---|
| 7 | EE | Cho W. Moon,
Harish Kriplani,
Krishna P. Belkhale:
Timing model extraction of hierarchical blocks by graph reduction.
DAC 2002: 152-157 |
| 1995 |
|---|
| 6 | EE | Luciano Lavagno,
Cho W. Moon,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
An efficient heuristic procedure for solving the state assignment problem for event-based specifications.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(1): 45-60 (1995) |
| 1994 |
|---|
| 5 | EE | Cho W. Moon,
Paul R. Stephan,
Robert K. Brayton:
Specification, synthesis, and verification of hazard-free asynchronous circuits.
VLSI Signal Processing 7(1-2): 85-100 (1994) |
| 1993 |
|---|
| 4 | EE | Cho W. Moon,
Robert K. Brayton:
Elimination of Dynamic hazards by Factoring.
DAC 1993: 7-13 |
| 1992 |
|---|
| 3 | EE | Luciano Lavagno,
Cho W. Moon,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Solving the State Assignment Problem for Signal Transition Graphs.
DAC 1992: 568-572 |
| 2 | | Ellen Sentovich,
Kanwar Jit Singh,
Cho W. Moon,
Hamid Savoj,
Robert K. Brayton,
Alberto L. Sangiovanni-Vincentelli:
Sequential Circuit Design Using Synthesis and Optimization.
ICCD 1992: 328-333 |
| 1991 |
|---|
| 1 | | Cho W. Moon,
Paul R. Stephan,
Robert K. Brayton:
Synthesis of Hazard-Free Asynchronous Circuits from Graphical Specifications.
ICCAD 1991: 322-325 |
