| 1995 |
|---|
| 8 | EE | So-Zen Yao,
Chung-Kuan Cheng,
Debaprosad Dutt,
Surendra Nahar,
Chi-Yuan Lo:
A cell-based hierarchical pitchmatching compaction using minimal LP.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 523-526 (1995) |
| 1993 |
|---|
| 7 | EE | So-Zen Yao,
Chung-Kuan Cheng,
Debaprosad Dutt,
Surendra Nahar,
Chi-Yuan Lo:
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP.
DAC 1993: 395-400 |
| 1989 |
|---|
| 6 | EE | Kuang-Wei Chiang,
Surendra Nahar,
Chi-Yuan Lo:
Time-efficient VLSI artwork analysis algorithms in GOALIE2.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 640-648 (1989) |
| 1988 |
|---|
| 5 | EE | Kuang-Wei Chiang,
Surendra Nahar,
Chi-Yuan Lo:
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2.
DAC 1988: 471-475 |
| 4 | EE | Surendra Nahar,
Sartaj K. Sahni:
Fast algorithm for polygon decomposition.
IEEE Trans. on CAD of Integrated Circuits and Systems 7(4): 473-483 (1988) |
| 1986 |
|---|
| 3 | EE | Surendra Nahar,
Sartaj Sahni,
Eugene Shragowitz:
Simulated annealing and combinatorial optimization.
DAC 1986: 293-299 |
| 2 | EE | Surendra Nahar,
Sartaj Sahni:
A time and space efficient net extractor.
DAC 1986: 411-417 |
| 1985 |
|---|
| 1 | EE | Surendra Nahar,
Sartaj Sahni,
Eugene Shragowitz:
Experiments with simulated annealing.
DAC 1985: 748-752 |
