| 2007 |
|---|
| 8 | EE | Masahiko Omura,
Toshiki Kanamoto,
Michiko Tsukamoto,
Mitsutoshi Shirota,
Takashi Nakajima,
Masayuki Terai:
A Fast Characterizing Method for Large Embedded Memory Modules on SoC.
IEICE Transactions 90-A(4): 815-822 (2007) |
| 2005 |
|---|
| 7 | EE | Toshiki Kanamoto,
Tetsuya Watanabe,
Mitsutoshi Shirota,
Masayuki Terai,
Tatsuya Kunikiyo,
Kiyoshi Ishikawa,
Yoshihide Ajioka,
Yasutaka Horiba:
A Method of Precise Estimation of Physical Parameters in LSI Interconnect Structures.
IEICE Transactions 88-A(12): 3463-3470 (2005) |
| 1995 |
|---|
| 6 | EE | Kazuhiro Takahashi,
Kazuo Nakajima,
Masayuki Terai,
Koji Sato:
Min-cut placement with global objective functions for large scale sea-of-gates arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 434-446 (1995) |
| 1994 |
|---|
| 5 | EE | Kazuhiro Takahashi,
Kazuo Nakajima,
Masayuki Terai,
Koji Sato:
Adaptive cut line selection in min-cut placement for large scale sea-of-gates arrays.
ICCAD 1994: 428-431 |
| 4 | EE | Masayuki Terai,
Kazuo Nakajima,
Kazuhiro Takahashi,
Koji Sato:
A new approach to over-the-cell channel routing with three layers.
IEEE Trans. on CAD of Integrated Circuits and Systems 13(2): 187-200 (1994) |
| 1991 |
|---|
| 3 | | Masayuki Terai,
Kazuhiro Takahashi,
Kazuo Nakajima,
Koji Sato:
A New Model for Over-The-Cell Channel Routing with Three Layers.
ICCAD 1991: 432-435 |
| 1990 |
|---|
| 2 | EE | Masayuki Terai,
Kazuhiro Takahashi,
Koji Sato:
A New Min-Cut Placement Algorithm for Timing Assurance Layout Design Meeting Net Length Constraint.
DAC 1990: 96-102 |
| 1985 |
|---|
| 1 | EE | Masayuki Terai:
A Method of Improving the Terminal Assignment in the Channel Routing for Gate Arrays.
IEEE Trans. on CAD of Integrated Circuits and Systems 4(3): 329-336 (1985) |
