| 2004 |
|---|
| 11 | EE | Stephen Bailey,
Erich Marschner,
Jayaram Bhasker,
Jim Lewis,
Peter J. Ashenden:
Improving Design and Verification Productivity with VHDL-200x.
DATE 2004: 332-335 |
| 1995 |
|---|
| 10 | EE | Muhammad K. Dhodhi,
Frank H. Hielscher,
Robert H. Storer,
Jayaram Bhasker:
Datapath synthesis using a problem-space genetic algorithm.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 934-944 (1995) |
| 1991 |
|---|
| 9 | EE | Rolf Ernst,
Jayaram Bhasker:
Simulation-Based Verification for High-Level Synthesis.
IEEE Design & Test of Computers 8(1): 14-20 (1991) |
| 1990 |
|---|
| 8 | EE | Jayaram Bhasker,
Huan-Chih Lee:
An Optimizer for Hardware Synthesis.
IEEE Design & Test of Computers 7(5): 20-36 (1990) |
| 1989 |
|---|
| 7 | | Jayaram Bhasker,
Sartaj Sahni:
Via Assignment in Single-Row Routing.
IEEE Trans. Computers 38(1): 142-149 (1989) |
| 1988 |
|---|
| 6 | | Jayaram Bhasker,
Sartaj Sahni:
A Linear Algorithm to Find a Rectangular Dual of a Planar Triangulated Graph.
Algorithmica 3: 247-278 (1988) |
| 5 | EE | Jayaram Bhasker:
Implementation of an optimizing compiler for VHDL.
SIGPLAN Notices 23(1): 92-108 (1988) |
| 4 | | Jayaram Bhasker:
Process-graph Analyser: A Front-end Tool for VHDL Behavioural Synthesis.
Softw., Pract. Exper. 18(5): 469-483 (1988) |
| 1987 |
|---|
| 3 | EE | Jayaram Bhasker:
An algorithm for microcode compaction of VHDL behavioral descriptions.
MICRO 1987: 54-58 |
| 2 | EE | Jayaram Bhasker,
Tariq Samad:
Compacting MIMOLA microcode.
MICRO 1987: 97-105 |
| 1986 |
|---|
| 1 | EE | Jayaram Bhasker,
Sartaj Sahni:
A linear algorithm to find a rectangular dual of a planar triangulated graph.
DAC 1986: 108-114 |
