| 1998 |
|---|
| 5 | EE | Tzu-Chieh Tien,
Hsiao-Pin Su,
Yu-Wen Tsay,
Yih-Chih Chou,
Youn-Long Lin:
Integrating logic retiming and register placement.
ICCAD 1998: 136-139 |
| 1997 |
|---|
| 4 | EE | Yu-Wen Tsay,
Wen-Jong Fang,
Allen C.-H. Wu,
Youn-Long Lin:
Preserving HDL synthesis hierarchy for cell placement.
ISPD 1997: 169-174 |
| 1995 |
|---|
| 3 | EE | Yu-Wen Tsay,
Youn-Long Lin:
A row-based cell placement method that utilizes circuit structural properties.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 393-397 (1995) |
| 2 | EE | Chau-Shen Chen,
Yu-Wen Tsay,
TingTing Hwang,
Allen C.-H. Wu,
Youn-Long Lin:
Combining technology mapping and placement for delay-minimization in FPGA designs.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1076-1084 (1995) |
| 1993 |
|---|
| 1 | EE | Chau-Shen Chen,
Yu-Wen Tsay,
TingTing Hwang,
Allen C.-H. Wu,
Youn-Long Lin:
Combining technology mapping and placement for delay-optimization in FPGA designs.
ICCAD 1993: 123-127 |
