| 1995 |
|---|
| 19 | EE | Anoop Singhal,
Chi-Yuan Lo:
Object oriented data modeling for VLSI/CAD.
VLSI Design 1995: 25-29 |
| 18 | EE | So-Zen Yao,
Chung-Kuan Cheng,
Debaprosad Dutt,
Surendra Nahar,
Chi-Yuan Lo:
A cell-based hierarchical pitchmatching compaction using minimal LP.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 523-526 (1995) |
| 1994 |
|---|
| 17 | | Chi-Yuan Lo,
Jirí Matousek,
William L. Steiger:
Algorithms for Ham-Sandwich Cuts.
Discrete & Computational Geometry 11: 433-452 (1994) |
| 16 | EE | Shun-Lin Su,
Charles H. Barry,
Chi-Yuan Lo:
A space-efficient short-finding algorithm [VLSI layouts].
IEEE Trans. on CAD of Integrated Circuits and Systems 13(8): 1065-1068 (1994) |
| 1993 |
|---|
| 15 | EE | So-Zen Yao,
Chung-Kuan Cheng,
Debaprosad Dutt,
Surendra Nahar,
Chi-Yuan Lo:
Cell-Based Hierarchical Pitchmatching Compaction Using Minimal LP.
DAC 1993: 395-400 |
| 14 | EE | Anoop Singhal,
Robert M. Arlein,
Chi-Yuan Lo:
DDB: An Object Oriented Design Data Manager for VLSI CAD.
SIGMOD Conference 1993: 467-470 |
| 13 | EE | Nishit P. Parikh,
Chi-Yuan Lo,
Anoop Singhal,
Kwok W. Wu:
HS: a hierarchical search package for CAD data.
IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 1-5 (1993) |
| 1992 |
|---|
| 12 | | Chi-Yuan Lo,
Jirí Matousek,
William L. Steiger:
Ham-Sandwich Cuts in R^d
STOC 1992: 539-545 |
| 11 | EE | Charles R. Bonapace,
Chi-Yuan Lo:
An O(n log m) algorithm for VLSI design rule checking.
IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 753-758 (1992) |
| 1991 |
|---|
| 10 | EE | Debaprosad Dutt,
Chi-Yuan Lo:
On Minimal Closure Constraint Generation for Symbolic Cell Assembly.
DAC 1991: 736-739 |
| 1990 |
|---|
| 9 | EE | Chi-Yuan Lo,
Ravi Varadarajan:
An O(n1.5logn) 1-d Compaction Algorithm.
DAC 1990: 382-387 |
| 8 | | Nishit P. Parikh,
Chi-Yuan Lo,
Anoop Singhal,
Kwok W. Wu:
HS: A Hierarchical Search Package for CAD Data.
ICCAD 1990: 478-481 |
| 1989 |
|---|
| 7 | EE | Chong-Leong Ong,
Jeong-Tyng Li,
Chi-Yuan Lo:
GENAC: An Automatic Cell Synthesis Tool.
DAC 1989: 239-244 |
| 6 | EE | H. Shin,
Chi-Yuan Lo:
An Efficient Two-Dimensional Layout Compaction Algorithm.
DAC 1989: 290-295 |
| 5 | EE | Chi-Yuan Lo:
Automatic Tub Region Generation for Symbolic Layout Compaction.
DAC 1989: 302-306 |
| 4 | EE | Charles R. Bonapace,
Chi-Yuan Lo:
An O(nlogm) Algorithm for VLSI Design Rule Checking.
DAC 1989: 503-507 |
| 3 | EE | Kuang-Wei Chiang,
Surendra Nahar,
Chi-Yuan Lo:
Time-efficient VLSI artwork analysis algorithms in GOALIE2.
IEEE Trans. on CAD of Integrated Circuits and Systems 8(6): 640-648 (1989) |
| 1988 |
|---|
| 2 | EE | Kuang-Wei Chiang,
Surendra Nahar,
Chi-Yuan Lo:
Time Efficient VLSI Artwork Analysis Algorithms in GOALIE2.
DAC 1988: 471-475 |
| 1987 |
|---|
| 1 | EE | Chi-Yuan Lo,
Hao N. Nham,
Ajoy K. Bose:
Algorithms for an Advanced Fault Simulation System in MOTIS.
IEEE Trans. on CAD of Integrated Circuits and Systems 6(2): 232-240 (1987) |
