| 1995 |
|---|
| 4 | EE | Soo Young Lee,
Kewal K. Saluja:
Test application time reduction for sequential circuits with scan.
IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1128-1140 (1995) |
| 1993 |
|---|
| 3 | | Soo Young Lee,
Kewal K. Saluja:
Efficient Test Vectors for ISCAS Sequential Benchmark Circuits.
ISCAS 1993: 1511-1514 |
| 2 | | Todd P. Kelsey,
Kewal K. Saluja,
Soo Young Lee:
An Efficient Algorithm for Sequential Circuit Test Generation.
IEEE Trans. Computers 42(11): 1361-1371 (1993) |
| 1992 |
|---|
| 1 | EE | Soo Young Lee,
Kewal K. Saluja:
An algorithm to reduce test application time in full scan designs.
ICCAD 1992: 17-20 |
