| |
| 1999 | ||
|---|---|---|
| 4 | EE | Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas: An algorithm for determining repetitive patterns in very large IC layouts. IEEE Trans. on CAD of Integrated Circuits and Systems 18(4): 494-501 (1999) |
| 1998 | ||
| 3 | EE | Mariusz Niewczas, Wojciech Maly, Andrzej J. Strojwas: A pattern matching algorithm for verification and analysis of very large IC layouts. ISPD 1998: 129-134 |
| 1997 | ||
| 2 | EE | Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz: Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation. VTS 1997: 172-176 |
| 1995 | ||
| 1 | EE | Mariusz Niewczas, Adam Wojtasik: Modeling of VLSI RC parasitics based on the network reduction algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 14(2): 137-144 (1995) |
| 1 | Zbigniew Jaworski | [2] |
| 2 | Wieslaw Kuzmicz | [2] |
| 3 | Wojciech Maly | [3] [4] |
| 4 | Andrzej J. Strojwas | [3] [4] |
| 5 | Adam Wojtasik | [1] |