ISCAS 2001:
Sydney,
Australia - Volume 4
International Symposium on Circuits and Systems (ISCAS 2001), 6-9 May 2001, Sydney, Australia.
IEEE 2001, ISBN 0-7803-6685-9 BibTeX
- Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang:
Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT.
1-4
Electronic Edition (link) BibTeX
- A. B. M. Harun-ur Rashid, M. Karim, S. M. Aziz:
Testing complementary pass-transistor logic circuits.
5-8
Electronic Edition (link) BibTeX
- S. L. Liu, S. Mourad, S. Krishnan:
At-speed testing of data communications transceivers.
9-12
Electronic Edition (link) BibTeX
- Shyue-Kung Lu, Chih-Hsien Hsu:
Built-In self-repair for divided word line memory.
13-16
Electronic Edition (link) BibTeX
- Abdelhakim Khouas, Anne Derieux:
FDP: fault detection probability function for analog circuits.
17-20
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- Z. M. Hussain, Boualem Boashash:
Statistical analysis of the time-delay digital tanlock loop in the presence of Gaussian noise.
21-24
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- Tung-Sang Ng, Kun-Wah Yip, Chin-Long Cheng:
An all-lag rotating-reference correlator and its efficient implementation.
25-28
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- Ki-Cheol Tae, Jin-Gyun Chung, Dae-Ik Kim:
Noise generation system using DCT.
29-32
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- Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
33-36
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- Johann Großschädl:
A low-power bit-serial multiplier for finite fields GF(2m).
37-40
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- A. C. McCormick, P. M. Grant, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan:
A low power MMSE receiver architecture for multi-carrier CDMA.
41-44
Electronic Edition (link) BibTeX
- U. Walther, G. P. Ferrweis:
PN-generators embedded in high performance signal processors.
45-48
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- T. Shimamura:
Nonuniform amplitude division for ABLMS equalisation.
49-52
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- D. Leon, Sina Balkir, Michael W. Hoffman, L. C. Perez:
Robust chaotic PN sequence generation techniques.
53-56
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- Yeong-Kang Lai, Yu-Chuan Shu:
VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation.
57-60
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- David Garrett, Mircea R. Stan:
A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications.
61-64
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- Zhipei Chi, Leilei Song, Keshab K. Parhi:
A study on the performance, complexity tradeoffs of block turbo decoder design.
65-68
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- Håkan Bengtson, Christer Svensson:
3V CMOS 0.35 µ transimpedance receiver for optical applications.
69-71
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- Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu:
A serial link transceiver for USB2 high-speed mode.
72-75
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- Inseop Lee, W. Kenneth Jenkins:
Pipelined implementation of the adaptive canceller-equalizer.
76-80
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- Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang:
A 1.25 GHz 32-bit tree-structured carry lookahead adder.
80-83
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- Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour:
A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder.
84-87
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- Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang:
A high-speed CMOS incrementer/decrementer.
88-91
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- Andreas Wassatsch, Dirk Timmermann:
Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC.
92-95
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- Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi:
A compact layout technique to minimize high frequency switching effects in high speed circuits.
96-99
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- H. Zarei, Omid Shoaei, Seid Mehdi Fakhraie:
A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis.
100-103
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- Xiaohong Sun, K. R. Laker:
A new design for cascaded sigma-delta modulators.
104-107
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- B. Voss, Manfred Glesner:
A low power sinusoidal clock.
108-111
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- Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo:
CML ring oscillators: oscillation frequency.
112-115
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- Yijun Zhou, Jiren Yuan:
An 8-Bit, 100-MHz low glitch interpolation DAC.
116-119
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- F. Xavier Moncunill-Geniz, O. Mas-Casals, Pere Palà-Schönwälder:
A comparative analysis of direct-sequence spread-spectrum super-regenerative architectures.
120-123
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- Kari Stadius, P. Jarvio, Petteri Paatsila, Kari Halonen:
Image-reject receivers with image-selection functionality.
124-127
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- Sridhar Rajagopal, Joseph R. Cavallaro:
A bit-streaming, pipelined multiuser detector for wireless communication receivers.
128-131
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- F. S. Tsai, Chen-Yi Lee:
A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system.
132-135
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- S. Makido, Takaya Yamazato, Hiraku Okada, Masaaki Katayama, Akira Ogawa:
A design of source matched MAP receiver for image transmission.
136-139
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- Yiannis Moisiadis, I. Bouras, Angela Arapoyanni:
A CMOS differential logic for low-power and high-speed applications.
140-143
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- Frank Grassert, Dirk Timmermann:
Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs.
144-147
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- Hongchin Lin, Yi-Fan Chen, Hsien-Chih She:
A low-power 3-phase half rail pass-gate differential logic.
148-151
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- K. Y. Cheung:
CRRDL: a novel charge recovery-recycling differential logic.
152-153
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- Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang:
Skew-tolerant high-speed (STHS) domino logic.
154-157
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- Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang:
Noise constrained power optimization for dual VT domino logic.
158-161
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- I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis:
The circuit design of multiple-valued logic voltage-mode adders.
162-165
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- Henrik Eriksson, Per Larsson-Edefors, William P. Marnane:
A regular parallel multiplier which utilizes multiple carry-propagate adders.
166-169
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- Pasi Liljeberg, Juha Plosila, Jouni Isoaho:
Asynchronous interface for locally clocked modules in ULSI systems.
170-173
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- Nazmy Abaskharoun, Mohamed Hafed, Gordon W. Roberts:
Strategies for on-chip sub-nanosecond signal capture and timing measurements.
174-177
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- Wen-Tsong Shiue:
Leakage power estimation and minimization in VLSI circuits.
178-181
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- Huo-Hsing Cheng, Ven-Chieh Hsieh:
A new logic synthesis and optimization procedure.
182-185
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- Artur Wróblewski, O. Schumecher, Christian V. Schimpfle, Josef A. Nossek:
Minimizing gate capacitances with transistor sizing.
186-189
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- Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang:
A low-cost CMOS time interval measurement core.
190-193
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- T. Santti, Jouni Isoaho:
Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units.
194-197
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- Felix Lustenberger, Hans-Andrea Loeliger:
On mismatch errors in analog-VLSI error correcting decoders.
198-201
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- Tong Zhang, Zhongfeng Wang, Keshab K. Parhi:
On finite precision implementation of low density parity check codes decoder.
202-205
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- Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders.
206-209
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- M. Traber:
A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros.
210-213
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- M. Traber:
A low power survivor memory unit for sequential Viterbi-Decoders.
214-217
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- Youngjoon Kim, Lee-Sup Kim:
A low power carry select adder with reduced area.
218-221
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- V. A. Bartlett, Andrew G. Dempster:
Using carry-save adders in low-power multiplier blocks.
222-225
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- Ayman A. Fayed, Magdy A. Bayoumi:
A low power 10-transistor full adder cell for embedded architectures.
226-229
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- Gang Xu, Jiren Yuan:
An embedded low power FIR filter.
230-233
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- S. Klauke, J. Gotze:
Low power enhancements for parallel algorithms.
234-237
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- Kasin Vichienchom, Mark Clements, Wentai Liu:
A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique.
238-241
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- R. K. Jain, R. Frenzel, M. Terschluse, P. K. Pandey, S. H. Low, B. Sukumaran, L. M. Lam:
System-on-chip design of a four-port ADSL-lite Data DSP.
242-245
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- Yuyu Chang, Jack Wills, John Choma Jr.:
On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters.
246-249
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- Chi-Li Yu, An-Yeu Wu:
An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter.
250-253
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- S. Huss, J. Bennett:
An efficient model for twisted-pair cables with discontinuities and stubs for discrete time simulations.
254-257
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- J. McEachen, Ow Kong Chung, Lim Chin Thong:
A system level description and model of Signaling System No 7.
258-261
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- Wael M. Badawy, Magdy A. Bayoumi:
A mesh based motion tracking architecture.
262-265
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- Jin-Ku Kang, Dong-Hee Kim:
A CMOS clock and data recovery with two-XOR phase-frequency detector circuit.
266-269
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- B. Siddik Yarman, Ahmet Aksen:
A reflectance-based computer aided modelling tool for high speed/high frequency communication systems.
270-273
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- Ronald P. Luijten, Antonius P. J. Engbersen, Cyriel Minkenberg:
Shared memory switching + virtual output queuing: A robust and scalable switch.
274-277
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- Mostafa I. Abd-El-Barr, C. Sundarram, A. S. Almulhem:
VLSI considerations in the design of k-ary n-cube interconnection networks.
278-281
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- Di He, Chen He, Ling-ge Jiang, Hong-Wen Zhu, Guang-Rui Hu:
Phase tracking of CDMA spreading sequences using dynamic chaotic synchronization.
282-285
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- Chin-Liang Wang, Ming-Hung Li, Kuo-Ming Wu, Kwei-Liang Hwang:
Adaptive interference suppression with power control for CDMA systems.
286-289
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- Kyungtae Han, Iksu Eo, Kyungsu Kim, Hanjin Cho:
Numerical word-length optimization for CDMA demodulator.
290-293
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- Jing Lei, Tung-Sang Ng:
New AFC algorithm for a fully-digital MDPSK DS/CDMA receiver.
294-297
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- X. M. Wang, Wu-Sheng Lu, Andreas Antoniou:
A near-optimal multiuser detector for CDMA channels using semidefinite programming relaxation.
298-301
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- Y. Bajot, H. Mehrez:
Customizable DSP architecture for ASIP core design.
302-305
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- T. S. Jarvinen, J. H. Takala, David Akopian, J. P. P. Saarinen:
Register-based multi-port perfect shuffle networks.
306-309
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- Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig:
Self-reorganising systems on VLSI circuits.
310-313
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- S. Mortezapour, E. K. F. Lee:
A reconfigurable pipelined data converter.
314-317
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- A. E. Bashagha:
Novel radix-2k division algorithm.
318-321
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- J. G. Lim, C. C. Lim:
A parallel architecture for estimating 4th-order cumulants.
322-325
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- Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee:
Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission.
326-329
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- Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee:
A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme.
330-333
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- Christos Drosos, Chrissavgi Dre, Spyros Blionas, Dimitrios Soudris:
On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal.
334-337
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- Li-Hsun Chen, Oscal T.-C. Chen:
A low-complexity and high-speed Booth-algorithm FIR architecture.
338-341
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- A.-O. Dahmane, Daniel Massicotte, Leszek Szczecinski:
A VLSI architecture of a piecewise RBF decision feedback channel equalizer.
342-345
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- Shyue-Win Wei:
Cellular-array power-sum circuits over programmable finite field GF(2''').
346-349
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- Marco Re, Alberto Nannarelli, Gian-Carlo Cardarilli, Roberto Lojacono:
FPGA realization of RNS to binary signed conversion architecture.
350-353
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- Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu:
Design and implementation of channel equalizers for block transmission systems.
354-357
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- Ching-Chi Chang, Chien-Chih Lin, Muh-Tian Shiue, Chorng-Kuang Wang:
A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop.
358-361
Electronic Edition (link) BibTeX
- W. Younis, Naofal Al-Dhahir:
FIR prefilter design for MLSE equalization of space-time-coded transmission over multipath fading channels.
362-365
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- R. Lopez-Valcarce, S. Dasgupta:
Second order statistics based blind channel equalization with correlated sources.
366-369
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- Ediz Çetin, Izzet Kale, Richard C. S. Morling:
Adaptive compensation of analog front-end I/Q mismatches in digital receivers.
370-373
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- Xiaopeng Li, Mohammed Ismail:
A single-chip CMOS front-end receiver architecture for multi-standard wireless applications.
374-377
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- Tang Jing Jung, King Sau Cheung, J. Lau:
A 2.4 GHz four port mixer for direct conversion used in telemetering.
378-381
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- Kalle Kivekäs, A. Parssinen, Jarkko Jussila, Jussi Ryynänen, Kari Halonen:
Design of low-voltage active mixer for direct conversion receivers.
382-385
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- Zhaofeng Zhang, L. Tsui, Zhiheng Chen, J. Lau:
A CMOS self-mixing-free front-end for direct conversion applications.
386-389
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- Hung Yan Cheung, King Sau Cheung, J. Lau:
A low power monolithic AGC with automatic DC offset cancellation for direct conversion hybrid CDMA transceiver used in telemetering.
390-393
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- Harri Lampinen, Olli Vainio:
Dynamically biased current sensor for current-sensing completion detection.
394-397
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- Yavuz Kiliç, Mark Zwolinski:
Process variation independent built-in current sensor for analogue built-in self-test.
398-401
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- Gaetano Palumbo, D. Pappalardo, M. Gaibotti:
Modeling and minimization of power consumption in charge pump circuits.
402-405
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- Sheng-Yeh Lai, Jinn-Shyan Wang:
A high-efficiency CMOS charge pump circuit.
406-409
Electronic Edition (link) BibTeX
- Joshua L. Garrett, Mircea R. Stan:
Active threshold compensation circuit for improved performance in cooled CMOS systems.
410-413
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- Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes:
Power trends and performance characterization of 3-dimensional integration.
414-417
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- Q. K. Zhu, M. Zhang:
Low-voltage swing clock distribution schemes.
418-421
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- Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.
422-425
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- Mohamed Nekili, Yvon Savaria, Guy Bois:
Minimizing process-induced skew using delay tuning.
426-429
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- Luca Fanucci, Roberto Roncella, Roberto Saletti:
Non-linearity reduction technique for delay-locked delay-lines.
430-433
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- Martin Makundi, Vesa Välimäki, Timo I. Laakso:
Closed-form design of tunable fractional-delay allpass filter structures.
434-437
Electronic Edition (link) BibTeX
- Shou-Sheu Lin, Wen-Rong Wu:
A low complexity adaptive interpolated FIR echo canceller.
438-441
Electronic Edition (link) BibTeX
- L. C. Chu, M. Brooke:
An enhancement study on the SDSL upstream receiver.
442-445
Electronic Edition (link) BibTeX
- Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh:
A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter.
446-449
Electronic Edition (link) BibTeX
- Thomas Magesacher, Per Ödling, T. Nordstrom, T. Lunberg, M. Isaksson, Per Ola Börjesson:
An adaptive mixed-signal narrowband interference canceller for wireline transmission systems.
450-453
Electronic Edition (link) BibTeX
- A. N. L. Chan, K. W. H. Ng, J. M. C. Wong, H. C. Luong:
A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application.
454-457
Electronic Edition (link) BibTeX
- Risto Kaunisto, P. Korpi, J. Kiraly, Kari Halonen:
A linear-control wide-band CMOS attenuator.
458-461
Electronic Edition (link) BibTeX
- Luca Fanucci, G. D'Angelo, A. Monterastelli, M. Paparo, B. Neri:
Fully integrated low-noise-amplifier with high quality factor L-C filter for 1.8 GHz wireless applications.
462-465
Electronic Edition (link) BibTeX
- J. C. Huang, Ro-Min Weng, Cheng-Chih Chang, Kang Hsu, Kun-Yi Lin:
A 2 V 2.4 GHz fully integrated CMOS LNA.
466-469
Electronic Edition (link) BibTeX
- Adiseno, M. Ismail, H. K. Olsson:
Dual-loop cross-coupled feedback amplifier for low-IF integrated receiver architecture.
470-473
Electronic Edition (link) BibTeX
- Mohamed A. Elgamel, Ahmed M. Shams, Xi Xueling, Magdy A. Bayoumi:
Enhanced low power motion estimation VLSI architectures for video compression.
474-477
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- Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen:
Interfacing multiple processors in a system-on-chip video encoder.
478-481
Electronic Edition (link) BibTeX
- Konstantina Karagianni, Thanos Stouraitis:
A vector processor for 3-D geometrical transformations.
482-485
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- Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny:
A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing.
486-489
Electronic Edition (link) BibTeX
- Piotr Dudek, P. J. Hicks:
An analogue SIMD focal-plane processor array.
490-493
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- Roberto Canegallo, D. Dozza, Roberto Guerrieri:
Low power techniques for flash memories.
494-497
Electronic Edition (link) BibTeX
- M. Jagasivamani, Dong Sam Ha:
Development of a low-power SRAM compiler.
498-501
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- William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria:
Fast system-level exploration of memory architectures driven by energy-delay metrics.
502-505
Electronic Edition (link) BibTeX
- A. Turier, L. Ben Ammar, Amara Amara:
Static power consumption management in CMOS memories.
506-509
Electronic Edition (link) BibTeX
- Byung-Do Yang, Lee-Sup Kim:
A low power charge-recycling ROM architecture.
510-513
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- Kah-Howe Tan, Wen Fung-Leong, S. Kadam, Michael A. Soderstrand, Louis G. Johnson:
Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation.
514-517
Electronic Edition (link) BibTeX
- Li-minn Ang, Hon Nin Cheung:
Hardware implementation of the depth first search bit stream SPIHT system.
518-521
Electronic Edition (link) BibTeX
- Ju Byoung Kim, Young Jin Lim, Moon Ho Lee:
A low complexity FEC design for DAB.
522-525
Electronic Edition (link) BibTeX
- S. L. Toral, J. M. Quero, M. E. Perez, Leopoldo García Franquelo:
A microprocessor based system for ECG telemedicine and telecare.
526-529
Electronic Edition (link) BibTeX
- Kuan-Hung Chen, Shi-Chung Chang, Tzi-Dar Chiueh, Peter B. Luh, Xing Zhao:
SIMD architecture for job shop scheduling problem solving.
530-533
Electronic Edition (link) BibTeX
- Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu:
A hardware design approach for merge-sorting network.
534-537
Electronic Edition (link) BibTeX
- Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-fat Chan:
A low power asynchronous DES.
538-541
Electronic Edition (link) BibTeX
- Chang-Ki Kwon, Kwyro Lee:
Reconfigurable and programmable minimum distance search engine for portable video compression systems.
542-545
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- K. Rajagopalan, P. Sutton:
A flexible multiplication unit for an FPGA logic block.
546-549
Electronic Edition (link) BibTeX
- Aiman H. El-Maleh, Yahya E. Osais:
A retiming-based test pattern generator design for built-in self test of data path architectures.
550-553
Electronic Edition (link) BibTeX
- V. K. Jain:
Hybrid wavelet/spread-spectrum system for broadband wireless LANs.
554-557
Electronic Edition (link) BibTeX
- Chien-Fang Hsu, Yuan-Hao Huang, Tzi-Dar Chiueh:
Design of an OFDM receiver for high-speed wireless LAN.
558-561
Electronic Edition (link) BibTeX
- A. Dhammika S. Jayalath, Chintha Tellambura:
Peak-to-average power ratio reduction of an OFDM signal using data permutation with embedded side information.
562-565
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- K. Sathananathan, Chintha Tellambura:
Forward error correction codes to reduce intercarrier interference in OFDM.
566-569
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- Jinwen Shentu, J. Armstrong:
Blind frequency offset estimation for PCC-OFDM with symbols overlapped in the time domain.
570-573
Electronic Edition (link) BibTeX
- Lijun Gao, Keshab K. Parhi:
Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec.
574-577
Electronic Edition (link) BibTeX
- Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee:
New bit-parallel systolic multipliers for a class of GF(2m).
578-581
Electronic Edition (link) BibTeX
- Sung-Won Lee, In-Cheol Park:
A low-power variable length decoder based on successive decoding of shoft codewords.
582-585
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- Mohammad K. Ibrahim, A. Almulhem:
Bit-level pipelined digit serial GF(2m) multiplier.
586-589
Electronic Edition (link) BibTeX
- Abdoul Rjoub, M. Alrousan, O. Jarrah, Odysseas G. Koufopavlou:
Multi-level low swing voltage values for low power design applications.
590-593
Electronic Edition (link) BibTeX
- P. R. van der Meer, Arie van Staveren:
Effectivity of standby-energy reduction techniques for deep sub-micron CMOS.
594-597
Electronic Edition (link) BibTeX
- T. R. Yasuda, M. Yamamoto, T. Nishi:
A power-on reset pulse generator for low voltage applications.
599-601
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- R. Becker:
Control loop for optimization of power consumption in VLSI designs.
602-605
Electronic Edition (link) BibTeX
- Byung G. Jo, J. Y. Kang, Myung Hoon Sunwoo:
A low power and area efficient FIR filter chip for PRML read channels.
606-609
Electronic Edition (link) BibTeX
- Lai-Kan Leung, Cheong-fat Chan, Oliver Chiu-sing Choy:
A giga-hertz CMOS digital controlled oscillator.
610-613
Electronic Edition (link) BibTeX
- Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung:
A low-power high driving ability voltage control oscillator used in PLL.
614-617
Electronic Edition (link) BibTeX
- T. Suutari, Jouni Isoaho, Hannu Tenhunen:
High-speed serial communication with error correction using 0.25 um CMOS technology.
618-621
Electronic Edition (link) BibTeX
- U. Singh, M. Green:
New structures for very high-frequency CMOS clock dividers.
622-625
Electronic Edition (link) BibTeX
- Antti Heiskanen, Antti Mäntyniemi, Timo Rahkonen:
A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level.
626-629
Electronic Edition (link) BibTeX
- Rui L. Aguiar, Dinis M. Santos:
Oscillatorless clock multiplication.
630-633
Electronic Edition (link) BibTeX
- Hong-Yi Huang, Teng-Neng Wang:
High-speed CMOS logic circuits in capacitor coupling technique.
634-637
Electronic Edition (link) BibTeX
- Mauro Olivieri, Alessandro Trifiletti:
An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores.
638-641
Electronic Edition (link) BibTeX
- Hamid Mahmoodi-Meimand, Ali Afzali-Kusha:
Efficient power clock generation for adiabatic logic.
642-645
Electronic Edition (link) BibTeX
- Natalia Kazakova, R. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux:
Fast and low-power inner product processor.
646-649
Electronic Edition (link) BibTeX
- Taek Won Kwon, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, Jun Rim Choi:
Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm.
650-653
Electronic Edition (link) BibTeX
- Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu:
Design of an efficient FFT processor for DAB system.
654-657
Electronic Edition (link) BibTeX
- Jiun-In Guo:
A low cost 2-D inverse discrete cosine transform design for image compression.
658-661
Electronic Edition (link) BibTeX
- Jiun-In Guo:
A new DA-based array for one dimensional discrete Hartley transform.
662-665
Electronic Edition (link) BibTeX
- Maw-Ching Liu, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou:
Low-power multiplierless FIR filter synthesizer based on CSD code.
666-669
Electronic Edition (link) BibTeX
- Chin-Liang Wang, Ching-Hsien Chang:
A new memory-based FFT processor for VDSL transceivers.
670-673
Electronic Edition (link) BibTeX
- S. Michael, R. Pieper:
A VLSI implementation of a universal programmable low sensitivity sampled data filter.
674-677
Electronic Edition (link) BibTeX
- Milena Stankovic, Radomir S. Stankovic, Jaakko Astola, Karen O. Egiazarian:
Circuit realization of spectral transforms in Fibonacci interconnection topologies.
678-681
Electronic Edition (link) BibTeX
- José M. Quintana, Maria J. Avedillo:
Reed-Muller descriptions of symmetric functions.
682-685
Electronic Edition (link) BibTeX
- J. L. Cura, Rui L. Aguiar:
Dynamic range boosting for wireless optical receivers.
686-689
Electronic Edition (link) BibTeX
- K. Miyashita, Y. S. Ichikawa, Y. Nakao, N. Shimataka, T. Otuki:
110 MHz IF-baseband CMOS receiver for J-CDMA/AMPS application.
690-693
Electronic Edition (link) BibTeX
- Jonghae Kim, Ramesh Harjani:
An ISM band CMOS integrated transceiver design for wireless telemetry system.
694-697
Electronic Edition (link) BibTeX
- Jaeyoung Shin, Joongho Choi, Jinup Lim, Sungwon Noh, Namil Baek, Jong-Hyeong Lee:
A 3.3-V analog front-end chip for HomePNA applications.
698-701
Electronic Edition (link) BibTeX
- Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo:
Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections.
702-705
Electronic Edition (link) BibTeX
- Ping Wu, Kai He:
A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications.
706-709
Electronic Edition (link) BibTeX
- Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee:
A wideband digital frequency synthesizer.
710-713
Electronic Edition (link) BibTeX
- Pietro Andreani:
A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor.
714-717
Electronic Edition (link) BibTeX
- Ming-Ta Hsieh, J. Harvey, R. Harjani:
Power optimization of CMOS LC VCOs.
718-721
Electronic Edition (link) BibTeX
- R. R.-B. Sheen, Oscal T.-C. Chen:
A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz.
722-725
Electronic Edition (link) BibTeX
- Panu Hämäläinen, Marko Hännikäinen, Timo Hämäläinen, Henk Corporaal, Jukka Saarinen:
Implementation of encryption algorithms on transport triggered architectures.
726-729
Electronic Edition (link) BibTeX
- D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis:
A CAD tool for architecture level exploration and automatic generation of RNS converters.
730-733
Electronic Edition (link) BibTeX
- Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa:
VLSI architecture of dynamically reconfigurable hardware-based cipher.
734-737
Electronic Edition (link) BibTeX
- S. Kawahitio, T. Eki, Y. Tadokoro:
A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform.
738-741
Electronic Edition (link) BibTeX
- Chris Howland, Andrew J. Blanksby:
Parallel decoding architectures for low density parity check codes.
742-745
Electronic Edition (link) BibTeX
- Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang:
Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology.
746-749
Electronic Edition (link) BibTeX
- Edgar F. M. Albuquerque, Manuel M. Silva:
Evaluation of substrate noise in CMOS and low-noise logic cells.
750-753
Electronic Edition (link) BibTeX
- Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win:
ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique.
754-757
Electronic Edition (link) BibTeX
- Ming-Dou Ker, Tung-Yang Chen:
Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes.
758-761
Electronic Edition (link) BibTeX
- I. Rovira, P. Sivonen, S. Rintamaki, M. Honkanen:
Highly linear TX IF-chip for multicarrier GSM 900 and 1800 base station.
762-765
Electronic Edition (link) BibTeX
- A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko, Dan Stiurca:
Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs.
766-769
Electronic Edition (link) BibTeX
- K. T. Christensen:
Design and optimization of CMOS switches for switched tuning of LC resonators.
770-773
Electronic Edition (link) BibTeX
- José Manuel de la Rosa, Maria Belen Pérez-Verdú, F. Medeiro, Rocio del Río, Ángel Rodríguez-Vázquez:
Analysis and experimental characterization of idle tones in 2nd-order bandpass Sigma-Delta modulators-a 0.8 um CMOS switched-current case study.
774-777
Electronic Edition (link) BibTeX
- K. T. Tiew, A. J. Payne, Peter Y. K. Cheung:
MASH delta-sigma modulators for wideband and multi-standard applications.
778-781
Electronic Edition (link) BibTeX
- Cheng-Chih Chang, Ro-Min Weng, J. C. Huang, Kang Hsu, Kun-Yi Lin:
A 1.5 V high gain CMOS mixer for 2.4-GHz applications.
782-785
Electronic Edition (link) BibTeX
- Jackson Harvey, Ramesh Harjani:
Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection.
786-789
Electronic Edition (link) BibTeX
- Sami Karvonen, Tom A. D. Riley, Juha Kostamovaara:
A low noise quadrature subsampling mixer.
790-793
Electronic Edition (link) BibTeX
- Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng:
A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage.
794-797
Electronic Edition (link) BibTeX
- M. E. S. Elrabaa, Mohamed I. Elmasry:
Split-Gate Logic circuits for multi-threshold technologies.
798-801
Electronic Edition (link) BibTeX
- Yiannis Moisiadis, A. I. Bouras, Angela Arapoyanni, Lampros Dermentzoglou:
A high-performance low-power static differential double edge-triggered flip-flop.
802-805
Electronic Edition (link) BibTeX
- Chulwoo Kim, Sung-Mo Kang:
A low-power reduced swing single clock flip-flop.
806-809
Electronic Edition (link) BibTeX
- Y. Fouzar, Yvon Savaria, Mohamad Sawan:
A new controlled gain phase-locked loop technique.
810-813
Electronic Edition (link) BibTeX
- Ian Brynjolfson, Zeljko Zilic:
A new PLL design for clock management applications.
814-817
Electronic Edition (link) BibTeX
- Takayuki Hamamoto, T. Wakamatsu, Kiyoharu Aizawa:
New method of on-sensor A/D conversion.
818-821
Electronic Edition (link) BibTeX
- Rachid Bouchakour, N. Harabech, P. Canet, Ph. Boivin, J. M. Mirabel:
Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect.
822-825
Electronic Edition (link) BibTeX
- Huiyun Li, Bah-Hwee Gwee, Joseph Sylvester Chang:
A digital Class D amplifier design embodying a novel sampling process and pulse generator.
826-829
Electronic Edition (link) BibTeX
- Marco Ottavi, Gian-Carlo Cardarilli, P. Marinucci, Salvatore Pontarelli, Adelio Salsano:
Development of a dynamic routing system for a fault tolerant solid state mass memory.
830-833
Electronic Edition (link) BibTeX
- Ye Lu, Mourad N. El-Gamal:
A 2.3 V low noise, low power, 10 GHz bandwidth Si-bipolar transimpedance preamplifier for optical receiver front-ends.
834-837
Electronic Edition (link) BibTeX
- Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin:
Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion.
838-841
Electronic Edition (link) BibTeX
- Tommy Kwong-Kin Tsang, Mourad N. El-Gamal:
A fully integrated 1 V 5.8 GHz bipolar LNA.
842-845
Electronic Edition (link) BibTeX
- P. Canet, Rachid Bouchakour, N. Harabech, Ph. Boivin, J. M. Mirabel:
EEPROM programming study-time and degradation aspects.
846-849
Electronic Edition (link) BibTeX
- S. I. Kayed, H. F. Ragaie, Mohamed Abou El-Ela, F. A. S. Soliman:
VLSI design and implementation of analog CMOS 2nd generation current conveyors.
850-853
Electronic Edition (link) BibTeX
- Yigang He, Yichuang Sun:
Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm.
854-857
Electronic Edition (link) BibTeX
- T. Ohira:
Emerging adaptive antenna techniques for wireless ad-hoc networks.
858-861
Electronic Edition (link) BibTeX
- K. Gyoda, Y. Kado, Y. Ohno, K. Hasuike, T. Ohira:
WACNet - Wireless Ad-hoc Community Network.
862-865
Electronic Edition (link) BibTeX
- T. Ogawa, E. Kudoh, H. Suda:
Multi-routing schemes for ad-hoc wireless networks.
866-869
Electronic Edition (link) BibTeX
- Hongjun Xu, Kyung Sup Kwak:
Space-time block coding for wireless ad hoc networks.
870-873
Electronic Edition (link) BibTeX
- Hiroshi Tamura, T. Moriyama, N. Matsumoto, Masakazu Sengoku, K. Mase, Shoji Shinoda:
Routing algorithms on wireless multihop networks and their modifications.
874-877
Electronic Edition (link) BibTeX
- Y. Dumonteix, Y. Bajot, H. Mehrez:
A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic.
878-881
Electronic Edition (link) BibTeX
- Chulwoo Kim, Ki-Wook Kim, Sung-Mo Kang:
Energy-efficient skewed static logic design with dual Vt.
882-885
Electronic Edition (link) BibTeX
- Rui Wang, Kaushik Roy, Cheng-Kok Koh:
Short-circuit power analysis of an inverter driving an RLC load.
886-889
Electronic Edition (link) BibTeX
- A. N. L. Chan, Chun Bing Guo, H. C. Luong:
A 1-V 2.4-GHz CMOS LNA with source degeneration as image-rejection notch filter.
890-893
Electronic Edition (link) BibTeX
- Kaoru Watanabe, Masakazu Sengoku, Hiroshi Tamura, Keisuke Nakano, Shoji Shinoda:
Graph problems in multi-hop networks.
894-897
Electronic Edition (link) BibTeX
- K. Mase, R. Noto, Keisuke Nakano, Keisuke Karasawa, Masakazu Sengoku, Shoji Shinoda:
A circuit-connection-based multihop wireless infrastructure for local communities.
898-901
Electronic Edition (link) BibTeX
- Jari Nikara, Jarmo Takala, David Akopian, Jukka Saarinen:
Pipeline architecture for DCT/IDCT.
902-905
Electronic Edition (link) BibTeX
- Minyi Fu, Vassil S. Dimitrov, Graham A. Jullien:
An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT.
906-909
Electronic Edition (link) BibTeX
- Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-fat Chan:
A pipelined dataflow small micro-coded asynchronous processor and its application to DCT.
910-913
Electronic Edition (link) BibTeX
- Tay-Jyi Lin, Chein-Wei Jen:
An efficient 2-D DWT architecture via resource cycling.
914-917
Electronic Edition (link) BibTeX
- Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai:
An LSI for VDD-hopping and MPEG4 system based on the chip.
918-921
Electronic Edition (link) BibTeX
- Vasily G. Moshnyaga, H. Tsuji:
Cache energy reduction by dual voltage supply.
922-925
Electronic Edition (link) BibTeX
- Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen:
Power modeling and low-power design of content addressable memories.
926-929
Electronic Edition (link) BibTeX
- T. Yamasaki, A. Suzuki, D. Kobayashi, T. Shibata:
A fast self-convergent flash-memory programming scheme for MV and analog data storage.
930-933
Electronic Edition (link) BibTeX
- Alessandro De Gloria, Mauro Olivieri:
An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors.
934-937
Electronic Edition (link) BibTeX
- Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures.
938-941
Electronic Edition (link) BibTeX
Copyright © Sat May 16 23:25:19 2009
by Michael Ley (ley@uni-trier.de)