Vasily G. Moshnyaga

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38 Vasily G. Moshnyaga: How to Really Save Computer Energy? CDES 2008: 89-95
37EEVasily G. Moshnyaga: Untraditional Approach to Computer Energy Reduction. PATMOS 2008: 82-92
36EEVasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak: Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh. ISCAS 2007: 2108-2111
35EEKoji Hashimoto, Vasily G. Moshnyaga, Kazuaki Murakami: Circuit Area-latency Optimization Technique for High-precision Elementary Functions. APCCAS 2006: 1406-1409
34EEVasily G. Moshnyaga, S. Yamaoka: MPEG complexity reduction by scene adaptive motion estimation. ISCAS 2006
33EEVasily G. Moshnyaga, Kenji Wakisaka: Reducing computations in MPEG2 video decoder. ISCAS 2006
32EEVasily G. Moshnyaga, Hoa Vo, Glenn Reinman, Miodrag Potkonjak: Handheld System Energy Reduction by OS-Driven Refresh. PATMOS 2006: 24-35
31 Vasily G. Moshnyaga, Naoki Migita, Kenji Wakisaka: Reduction of MPEG2 video decoding computations. Circuits, Signals, and Systems 2005: 218-221
30EEVasily G. Moshnyaga, Eiji Morikawa: LCD Display Energy Reduction by User Monitoring. ICCD 2005: 94-97
29EEVasily G. Moshnyaga, Eiji Morikawa: Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring. PATMOS 2005: 528-539
28EEVasily G. Moshnyaga, Tomoyuki Yamanaka: Multiplier Energy Reduction by Dynamic Voltage Variation. IEICE Transactions 88-A(12): 3548-3553 (2005)
27EEReiko Komiya, Koji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches. IEICE Transactions 88-A(4): 862-868 (2005)
26EEKentaro Hamayasu, Vasily G. Moshnyaga: Impact of Register-Cache Bandwidth Variation on Processor Performance. Asia-Pacific Computer Systems Architecture Conference 2004: 212-225
25 Tomoyuki Yamanaka, Vasily G. Moshnyaga: Reducing multiplier energy by data-driven voltage variation. ISCAS (2) 2004: 285-288
24EEVasily G. Moshnyaga, Koichi Masunaga, Naoki Kajiwara: A data reusing architecture for MPEG video coding. ISCAS (3) 2004: 797-800
23EEHiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Reducing Access Count to Register-Files through Operand Reuse. Asia-Pacific Computer Systems Architecture Conference 2003: 112-121
22EEMasayoshi Fujino, Vasily G. Moshnyaga: Dynamic operand transformation for low-power multiplier-accumulator design. ISCAS (5) 2003: 345-348
21EEVasily G. Moshnyaga: Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits. VLSI Signal Processing 33(1-2): 75-82 (2003)
20EEKoji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Reducing power consumption of instruction ROMs by exploiting instruction frequency. APCCAS (2) 2002: 1-6
19EEJun-ni Ohban, Vasily G. Moshnyaga, Koji Inoue: Multiplier energy reduction through bypassing of partial products. APCCAS (2) 2002: 13-17
18EEKoji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A Low Energy Set-Associative I-Cache with Extended BTB. ICCD 2002: 187-
17EEVasily G. Moshnyaga, Koji Inoue, Mizuka Fukagawa: Reducing energy consumption of video memory by bit-width compression. ISLPED 2002: 142-147
16EEKoji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: A history-based I-cache for low-energy multimedia applications. ISLPED 2002: 148-153
15EEKoji Inoue, Vasily G. Moshnyaga, Kazuaki Murakami: Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints. PACS 2002: 18-32
14EEHiroshi Takamura, Koji Inoue, Vasily G. Moshnyaga: Register File Energy Reduction by Operand Data Reuse. PATMOS 2002: 278-288
13 Vasily G. Moshnyaga: Reducing energy dissipation of frame memory by adaptive bit-width compression. IEEE Trans. Circuits Syst. Video Techn. 12(8): 713- (2002)
12EEVasily G. Moshnyaga: Reducing cache engery through dual voltage supply. ASP-DAC 2001: 302-305
11EEVasily G. Moshnyaga, H. Tsuji: Cache energy reduction by dual voltage supply. ISCAS (4) 2001: 922-925
10EEVasily G. Moshnyaga: Energy reduction in queues and stacks by adaptive bitwidth compression. ISLPED 2001: 22-27
9 Vasily G. Moshnyaga: A new computationally adaptive formulation of block-matching motion estimation. IEEE Trans. Circuits Syst. Video Techn. 11(1): 118-124 (2001)
8EEVasily G. Moshnyaga: A new architecture for computationally adaptive full-search block-matching motion estimation. ISCAS (4) 1999: 219-222
7EEVasily G. Moshnyaga: An MSB truncation scheme for low-power video processors. ISCAS (4) 1999: 291-294
6EEVasily G. Moshnyaga, Naoto Watanabe, Keikichi Tamaru: A memory efficient array architecture for real-time motion estimation. Systems and Computers in Japan 29(9): 13-20 (1998)
5EEVasily G. Moshnyaga, Keikichi Tamaru: A Memory Efficient Array Architecture for Real-Time Motion Estimation. IPPS 1997: 28-32
4EEVasily G. Moshnyaga, Fumiaki Ohbayashi, Keikichi Tamaru: A scheduling algorithm for synthesis of bus-partitioned architectures. ASP-DAC 1995
3 Vasily G. Moshnyaga, Keikichi Tamaru: A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers. ISCAS 1995: 1560-1563
2EEVasily G. Moshnyaga, Hiroshi Mori, Hidetoshi Onodera, Keikichi Tamaru: Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's. ICCAD 1993: 100-103
1 Vasily G. Moshnyaga, Keikichi Tamaru, Hiroto Yasuura: Design of data-path module generators from algorithmic representations. Synthesis for Control Dominated Circuits 1992: 183-192

Coauthor Index

1Masayoshi Fujino [22]
2Mizuka Fukagawa [17]
3Kentaro Hamayasu [26]
4Koji Hashimoto [35]
5Koji Inoue [14] [15] [16] [17] [18] [19] [20] [23] [27]
6Naoki Kajiwara [24]
7Reiko Komiya [27]
8Koichi Masunaga [24]
9Naoki Migita [31]
10Hiroshi Mori [2]
11Eiji Morikawa [29] [30]
12Kazuaki Murakami [15] [16] [18] [20] [27] [35]
13Jun-ni Ohban [19]
14Fumiaki Ohbayashi [4]
15Hidetoshi Onodera [2]
16Miodrag Potkonjak [32] [36]
17Glenn Reinman [32] [36]
18Hiroshi Takamura [14] [23]
19Keikichi Tamaru [1] [2] [3] [4] [5] [6]
20H. Tsuji [11]
21Hoa Vo [32]
22Hua Vo [36]
23Kenji Wakisaka [31] [33]
24Naoto Watanabe [6]
25Tomoyuki Yamanaka [25] [28]
26S. Yamaoka [34]
27Hiroto Yasuura [1]

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Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)