| 2008 |
|---|
| 38 | | Vasily G. Moshnyaga:
How to Really Save Computer Energy?
CDES 2008: 89-95 |
| 37 | EE | Vasily G. Moshnyaga:
Untraditional Approach to Computer Energy Reduction.
PATMOS 2008: 82-92 |
| 2007 |
|---|
| 36 | EE | Vasily G. Moshnyaga,
Hua Vo,
Glenn Reinman,
Miodrag Potkonjak:
Reducing Energy of DRAM/Flash Memory System by OS-controlled Data Refresh.
ISCAS 2007: 2108-2111 |
| 2006 |
|---|
| 35 | EE | Koji Hashimoto,
Vasily G. Moshnyaga,
Kazuaki Murakami:
Circuit Area-latency Optimization Technique for High-precision Elementary Functions.
APCCAS 2006: 1406-1409 |
| 34 | EE | Vasily G. Moshnyaga,
S. Yamaoka:
MPEG complexity reduction by scene adaptive motion estimation.
ISCAS 2006 |
| 33 | EE | Vasily G. Moshnyaga,
Kenji Wakisaka:
Reducing computations in MPEG2 video decoder.
ISCAS 2006 |
| 32 | EE | Vasily G. Moshnyaga,
Hoa Vo,
Glenn Reinman,
Miodrag Potkonjak:
Handheld System Energy Reduction by OS-Driven Refresh.
PATMOS 2006: 24-35 |
| 2005 |
|---|
| 31 | | Vasily G. Moshnyaga,
Naoki Migita,
Kenji Wakisaka:
Reduction of MPEG2 video decoding computations.
Circuits, Signals, and Systems 2005: 218-221 |
| 30 | EE | Vasily G. Moshnyaga,
Eiji Morikawa:
LCD Display Energy Reduction by User Monitoring.
ICCD 2005: 94-97 |
| 29 | EE | Vasily G. Moshnyaga,
Eiji Morikawa:
Reducing Energy Consumption of Computer Display by Camera-Based User Monitoring.
PATMOS 2005: 528-539 |
| 28 | EE | Vasily G. Moshnyaga,
Tomoyuki Yamanaka:
Multiplier Energy Reduction by Dynamic Voltage Variation.
IEICE Transactions 88-A(12): 3548-3553 (2005) |
| 27 | EE | Reiko Komiya,
Koji Inoue,
Vasily G. Moshnyaga,
Kazuaki Murakami:
Quantitative Evaluation of State-Preserving Leakage Reduction Algorithm for L1 Data Caches.
IEICE Transactions 88-A(4): 862-868 (2005) |
| 2004 |
|---|
| 26 | EE | Kentaro Hamayasu,
Vasily G. Moshnyaga:
Impact of Register-Cache Bandwidth Variation on Processor Performance.
Asia-Pacific Computer Systems Architecture Conference 2004: 212-225 |
| 25 | | Tomoyuki Yamanaka,
Vasily G. Moshnyaga:
Reducing multiplier energy by data-driven voltage variation.
ISCAS (2) 2004: 285-288 |
| 24 | EE | Vasily G. Moshnyaga,
Koichi Masunaga,
Naoki Kajiwara:
A data reusing architecture for MPEG video coding.
ISCAS (3) 2004: 797-800 |
| 2003 |
|---|
| 23 | EE | Hiroshi Takamura,
Koji Inoue,
Vasily G. Moshnyaga:
Reducing Access Count to Register-Files through Operand Reuse.
Asia-Pacific Computer Systems Architecture Conference 2003: 112-121 |
| 22 | EE | Masayoshi Fujino,
Vasily G. Moshnyaga:
Dynamic operand transformation for low-power multiplier-accumulator design.
ISCAS (5) 2003: 345-348 |
| 21 | EE | Vasily G. Moshnyaga:
Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits.
VLSI Signal Processing 33(1-2): 75-82 (2003) |
| 2002 |
|---|
| 20 | EE | Koji Inoue,
Vasily G. Moshnyaga,
Kazuaki Murakami:
Reducing power consumption of instruction ROMs by exploiting instruction frequency.
APCCAS (2) 2002: 1-6 |
| 19 | EE | Jun-ni Ohban,
Vasily G. Moshnyaga,
Koji Inoue:
Multiplier energy reduction through bypassing of partial products.
APCCAS (2) 2002: 13-17 |
| 18 | EE | Koji Inoue,
Vasily G. Moshnyaga,
Kazuaki Murakami:
A Low Energy Set-Associative I-Cache with Extended BTB.
ICCD 2002: 187- |
| 17 | EE | Vasily G. Moshnyaga,
Koji Inoue,
Mizuka Fukagawa:
Reducing energy consumption of video memory by bit-width compression.
ISLPED 2002: 142-147 |
| 16 | EE | Koji Inoue,
Vasily G. Moshnyaga,
Kazuaki Murakami:
A history-based I-cache for low-energy multimedia applications.
ISLPED 2002: 148-153 |
| 15 | EE | Koji Inoue,
Vasily G. Moshnyaga,
Kazuaki Murakami:
Dynamic Tag-Check Omission: A Low Power Instruction Cache Architecture Exploiting Execution Footprints.
PACS 2002: 18-32 |
| 14 | EE | Hiroshi Takamura,
Koji Inoue,
Vasily G. Moshnyaga:
Register File Energy Reduction by Operand Data Reuse.
PATMOS 2002: 278-288 |
| 13 | | Vasily G. Moshnyaga:
Reducing energy dissipation of frame memory by adaptive bit-width compression.
IEEE Trans. Circuits Syst. Video Techn. 12(8): 713- (2002) |
| 2001 |
|---|
| 12 | EE | Vasily G. Moshnyaga:
Reducing cache engery through dual voltage supply.
ASP-DAC 2001: 302-305 |
| 11 | EE | Vasily G. Moshnyaga,
H. Tsuji:
Cache energy reduction by dual voltage supply.
ISCAS (4) 2001: 922-925 |
| 10 | EE | Vasily G. Moshnyaga:
Energy reduction in queues and stacks by adaptive bitwidth compression.
ISLPED 2001: 22-27 |
| 9 | | Vasily G. Moshnyaga:
A new computationally adaptive formulation of block-matching motion estimation.
IEEE Trans. Circuits Syst. Video Techn. 11(1): 118-124 (2001) |
| 1999 |
|---|
| 8 | EE | Vasily G. Moshnyaga:
A new architecture for computationally adaptive full-search block-matching motion estimation.
ISCAS (4) 1999: 219-222 |
| 7 | EE | Vasily G. Moshnyaga:
An MSB truncation scheme for low-power video processors.
ISCAS (4) 1999: 291-294 |
| 1998 |
|---|
| 6 | EE | Vasily G. Moshnyaga,
Naoto Watanabe,
Keikichi Tamaru:
A memory efficient array architecture for real-time motion estimation.
Systems and Computers in Japan 29(9): 13-20 (1998) |
| 1997 |
|---|
| 5 | EE | Vasily G. Moshnyaga,
Keikichi Tamaru:
A Memory Efficient Array Architecture for Real-Time Motion Estimation.
IPPS 1997: 28-32 |
| 1995 |
|---|
| 4 | EE | Vasily G. Moshnyaga,
Fumiaki Ohbayashi,
Keikichi Tamaru:
A scheduling algorithm for synthesis of bus-partitioned architectures.
ASP-DAC 1995 |
| 3 | | Vasily G. Moshnyaga,
Keikichi Tamaru:
A Comparative Study of Switching Activity Reduction Techniques for Design of Low-Power Multipliers.
ISCAS 1995: 1560-1563 |
| 1993 |
|---|
| 2 | EE | Vasily G. Moshnyaga,
Hiroshi Mori,
Hidetoshi Onodera,
Keikichi Tamaru:
Layout-driven module selection for register-transfer synthesis of sub-micron ASIC's.
ICCAD 1993: 100-103 |
| 1992 |
|---|
| 1 | | Vasily G. Moshnyaga,
Keikichi Tamaru,
Hiroto Yasuura:
Design of data-path module generators from algorithmic representations.
Synthesis for Control Dominated Circuits 1992: 183-192 |
