| 2005 |
|---|
| 11 | EE | A. Landry,
Mohamed Nekili,
Yvon Savaria:
A novel 2 GHz multi-layer AMBA high-speed bus interconnect matrix for SoC platforms.
ISCAS (4) 2005: 3343-3346 |
| 10 | EE | Haydar Saaied,
Dhamin Al-Khalili,
Asim J. Al-Khalili,
Mohamed Nekili:
Simultaneous adaptive wire adjustment and local topology modification for tuning a bounded-skew clock tree.
IEEE Trans. on CAD of Integrated Circuits and Systems 24(10): 1637-1643 (2005) |
| 2004 |
|---|
| 9 | EE | Adhir Upadhyay,
Syed Rafay Hasan,
Mohamed Nekili:
Optimal partitioning of globally asychronous locally synchronous processor arrays.
ACM Great Lakes Symposium on VLSI 2004: 7-12 |
| 2002 |
|---|
| 8 | EE | Falah R. Awwad,
Mohamed Nekili:
Variable-segment & variable-driver parallel regeneration techniques for RLC VLSI interconnects.
ACM Great Lakes Symposium on VLSI 2002: 118-123 |
| 7 | EE | Bill Pontikakis,
Mohamed Nekili:
A novel double edge-triggered pulse-clocked TSPC D flip-flop for high-performance and low-power VLSI design applications.
ISCAS (5) 2002: 101-104 |
| 6 | EE | Haydar Saaied,
Dhamin Al-Khalili,
Asim J. Al-Khalili,
Mohamed Nekili:
Quadratic deferred-merge embedding algorithm for zero skew clock distribution network.
Timing Issues in the Specification and Synthesis of Digital Systems 2002: 119-125 |
| 2001 |
|---|
| 5 | EE | Mohamed Nekili,
Yvon Savaria,
Guy Bois:
Minimizing process-induced skew using delay tuning.
ISCAS (4) 2001: 426-429 |
| 1998 |
|---|
| 4 | EE | Mohamed Nekili,
Yvon Savaria,
Guy Bois:
Design of Clock Distribution Networks in Presence of Process Variations.
Great Lakes Symposium on VLSI 1998: 95-102 |
| 1997 |
|---|
| 3 | EE | Mohamed Nekili,
Guy Bois,
Yvon Savaria:
Pipelined H-trees for high-speed clocking of large integrated systems in presence of process variations.
IEEE Trans. VLSI Syst. 5(2): 161-174 (1997) |
| 1994 |
|---|
| 2 | | Mohamed Nekili,
Yvon Savaria,
Guy Bois:
A Fast Low-Power Driver for Long Interconnections in VLSI Systems.
ISCAS 1994: 343-346 |
| 1993 |
|---|
| 1 | | Mohamed Nekili,
Yvon Savaria:
Parallel Regeneration of Interconnections in VLSI & ULSI Circuits.
ISCAS 1993: 2023-2026 |
