2008 |
26 | | Tomi Metsälä,
Tomi Westerlund,
Seppo Virtanen,
Juha Plosila:
Rigorous Communication Modelling at Transaction Level With Systemc.
ICSOFT (SE/MUSE/GSDCA) 2008: 246-251 |
25 | EE | Tero Säntti,
Joonas Tyystjärvi,
Juha Plosila:
A novel hardware acceleration scheme for java method calls.
ISCAS 2008: 1676-1679 |
24 | EE | Ethiopia Nigussie,
Juha Plosila,
Jouni Isoaho:
Area efficient delay-insensitive and differential current sensing on-chip interconnect.
SoCC 2008: 143-146 |
23 | EE | Johanna Tuominen,
Tomi Westerlund,
Juha Plosila:
Power Aware System Refinement.
Electr. Notes Theor. Comput. Sci. 201: 223-253 (2008) |
2007 |
22 | EE | Teijo Lehtonen,
Pasi Liljeberg,
Juha Plosila:
Fault Tolerance Analysis of NoC Architectures.
ISCAS 2007: 361-364 |
21 | EE | Ethiopia Nigussie,
Juha Plosila,
Jouni Isoaho:
Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail Encoding.
ISCAS 2007: 649-652 |
20 | EE | Tomi Westerlund,
Juha Plosila:
Time Aware System Refinement.
Electr. Notes Theor. Comput. Sci. 187: 91-106 (2007) |
2006 |
19 | EE | Tomi Westerlund,
Juha Plosila:
Time Aware Modelling and Analysis of Multiclocked VLSI Systems.
ICFEM 2006: 737-756 |
18 | EE | Teijo Lehtonen,
Pekka Rantala,
P. Isomaki,
Juha Plosila,
Jouni Isoaho:
An approach for analysing and improving fault tolerance in radio architectures.
ISCAS 2006 |
17 | EE | Ethiopia Nigussie,
Juha Plosila,
Jouni Isoaho:
Full-duplex link implementation using dual-rail encoding and multiple-valued current-mode logic.
ISCAS 2006 |
16 | EE | Ethiopia Nigussie,
Juha Plosila,
Jouni Isoaho:
Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling.
ISVLSI 2006: 217-224 |
15 | EE | Zheng Liang,
Juha Plosila,
Lu Yan,
Kaisa Sere:
Implementing a Self-Timed Low-Power Java Accelerator for Network-on-Chip Applications.
PDCAT 2006: 344-347 |
2005 |
14 | EE | Juha Plosila,
Pasi Liljeberg,
Jouni Isoaho:
Modelling and Refinement of an On-Chip Communication Architecture.
ICFEM 2005: 219-234 |
13 | EE | Zheng Liang,
Juha Plosila,
Lu Yan,
Kaisa Sere:
On-chip Debug for an Asynchronous Java Accelerator.
PDCAT 2005: 312-315 |
12 | EE | Tomi Westerlund,
Juha Plosila:
Formal Specification of a Protocol Processor.
SAMOS 2005: 122-131 |
11 | EE | Juha Plosila,
Kaisa Sere,
Marina A. Waldén:
Asynchronous system synthesis.
Sci. Comput. Program. 55(1-3): 259-288 (2005) |
2004 |
10 | EE | Tiberiu Seceleanu,
Juha Plosila:
Constituent Elements of a Correctness-Preserving UML Design Approach.
IFM 2004: 227-246 |
9 | EE | Pasi Liljeberg,
Juha Plosila,
Jouni Isoaho:
Self-timed communication platform for implementing high-performance systems-on-chip.
Integration 38(1): 43-67 (2004) |
2003 |
8 | EE | Juha Plosila,
Tiberiu Seceleanu,
Pasi Liljeberg:
Implementation of a Self-Timed Segmented Bus.
IEEE Design & Test of Computers 20(6): 44-50 (2003) |
2002 |
7 | EE | Juha Plosila,
Kaisa Sere,
Marina A. Waldén:
Design with Asynchronously Communicating Components.
FMCO 2002: 424-442 |
6 | EE | Juha Plosila,
Tiberiu Seceleanu:
Specification of an Asynchronous On-chip Bus.
ICFEM 2002: 383-395 |
5 | EE | Pasi Liljeberg,
Imed Ben Dhaou,
Juha Plosila,
Jouni Isoaho,
Hannu Tenhunen:
Interconnect peak current reduction for wavelet array processor using self-timed signaling.
ISCAS (4) 2002: 485-488 |
2001 |
4 | EE | Tiberiu Seceleanu,
Juha Plosila:
Formal Pipeline Design.
CHARME 2001: 167-172 |
3 | EE | Pasi Liljeberg,
Juha Plosila,
Jouni Isoaho:
Asynchronous interface for locally clocked modules in ULSI systems.
ISCAS (4) 2001: 170-173 |
2000 |
2 | EE | Juha Plosila,
Tiberiu Seceleanu:
Design of Synchronous Action Systems.
VLSI Design 2000: 578-583 |
1997 |
1 | EE | Juha Plosila,
Kaisa Sere:
Action Systems in Pipelined Processor Design.
ASYNC 1997: 156-166 |