| 2009 |
|---|
| 45 | EE | Yang Sun,
Joseph R. Cavallaro:
High throughput VLSI architecture for soft-output mimo detection based on a greedy graph algorithm.
ACM Great Lakes Symposium on VLSI 2009: 445-450 |
| 2008 |
|---|
| 44 | EE | Yang Sun,
Yuming Zhu,
Manish Goel,
Joseph R. Cavallaro:
Configurable and scalable high throughput turbo decoder architecture for multiple 4G wireless standards.
ASAP 2008: 209-214 |
| 43 | EE | Kiarash Amiri,
Davood Shamsi,
Behnaam Aazhang,
Joseph R. Cavallaro:
Adaptive codebook for beamforming in limited feedback MIMO systems.
CISS 2008: 994-998 |
| 42 | EE | Predrag Radosavljevic,
Kyeong Jin Kim,
Joseph R. Cavallaro:
QRD-QLD Searching Based Sphere Detection for Emerging MIMO Downlink OFDM Receivers.
GLOBECOM 2008: 4212-4216 |
| 41 | EE | Kiarash Amiri,
Chris Dick,
Raghu Rao,
Joseph R. Cavallaro:
Novel Sort-Free Detector with Modified Real-Valued Decomposition (M-RVD) Ordering in MIMO Systems.
GLOBECOM 2008: 4217-4221 |
| 40 | EE | Yang Sun,
Joseph R. Cavallaro:
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards.
SoCC 2008: 367-370 |
| 39 | EE | Marjan Karkooti,
Joseph R. Cavallaro:
Cooperative Communications Using Scalable, Medium Block-length LDPC Codes.
WCNC 2008: 88-93 |
| 38 | EE | Sridhar Rajagopal,
Joseph R. Cavallaro:
Communication Processors for Wireless Systems.
Wiley Encyclopedia of Computer Science and Engineering 2008 |
| 37 | EE | Vikram Chandrasekhar,
Frank Livingston,
Joseph R. Cavallaro:
Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers.
IJES 3(3): 128-140 (2008) |
| 36 | EE | Marjan Karkooti,
Predrag Radosavljevic,
Joseph R. Cavallaro:
Configurable LDPC Decoder Architectures for Regular and Irregular Codes.
Signal Processing Systems 53(1-2): 73-88 (2008) |
| 2007 |
|---|
| 35 | EE | Markus Myllylä,
Markku J. Juntti,
Joseph R. Cavallaro:
Implementation Aspects of List Sphere Detector Algorithms.
GLOBECOM 2007: 3915-3920 |
| 34 | EE | Yang Sun,
Marjan Karkooti,
Joseph R. Cavallaro:
VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes.
ISCAS 2007: 2104-2107 |
| 33 | EE | Joseph R. Cavallaro,
Sanjay Rajopadhye,
Lothar Thiele,
Tobias Noll:
Special Issue on ASAP 2004 Conference.
VLSI Signal Processing 49(1): 1-2 (2007) |
| 2006 |
|---|
| 32 | EE | Marjan Karkooti,
Predrag Radosavljevic,
Joseph R. Cavallaro:
Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation.
ASAP 2006: 360-367 |
| 31 | EE | Sridhar Rajagopal,
Joseph R. Cavallaro:
Truncated Online Arithmetic with Applications to Communication Systems.
IEEE Trans. Computers 55(10): 1240-12529 (2006) |
| 30 | EE | Panagiotis Demestichas,
Guillaume Vivier,
Joseph R. Cavallaro:
Special Issue on Reconfigurable Radio Technologies in Support of Ubiquitous Seamless Computing.
MONET 11(6): 775-777 (2006) |
| 29 | EE | Yuanbin Guo,
Joseph R. Cavallaro:
A Low Complexity and Low Power SoC Design Architecture for Adaptive MAI Suppression in CDMA Systems.
VLSI Signal Processing 44(3): 195-217 (2006) |
| 2005 |
|---|
| 28 | EE | Manik Gadhiok,
Ricky Hardy,
Patrick Murphy,
J. Patrick Frantz,
Hyeokho Choi,
Joseph R. Cavallaro:
An FPGA-Based Daughtercard for TI's C6000 family of DSKs.
MSE 2005: 85-86 |
| 27 | EE | S. Das,
Elza Erkip,
Joseph R. Cavallaro,
Behnaam Aazhang:
Low-complexity iterative multiuser detection and decoding for real-time applications.
IEEE Transactions on Wireless Communications 4(4): 1455-1460 (2005) |
| 2004 |
|---|
| 26 | | Yuanbin Guo,
Dennis McCain,
Joseph R. Cavallaro:
Low complexity System-on-Chip architectures of Parallel-Residue-Compensation in CDMA systems.
ISCAS (4) 2004: 77-80 |
| 25 | EE | Marjan Karkooti,
Joseph R. Cavallaro:
Semi-Parallel Reconfigurable Architectures for Real-Time LDPC Decoding.
ITCC (1) 2004: 579-585 |
| 24 | EE | Sridhar Rajagopal,
Joseph R. Cavallaro,
Scott Rixner:
Design Space Exploration for Real-Time Embedded Stream Processors.
IEEE Micro 24(4): 54-66 (2004) |
| 2003 |
|---|
| 23 | EE | Vikram Chandrasekhar,
Frank Livingston,
Joseph R. Cavallaro:
Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers.
ASAP 2003: 260-270 |
| 22 | EE | Yuanbin Guo,
Gang Xu,
Dennis McCain,
Joseph R. Cavallaro:
Rapid Scheduling of Efficient VLSI Architectures for Next-Generation HSDPA.
IEEE International Workshop on Rapid System Prototyping 2003: 179-185 |
| 21 | EE | Patrick Murphy,
J. Patrick Frantz,
Erik Welsh,
Ricky Hardy,
Tinoosh Mohsenin,
Joseph R. Cavallaro:
VALID: Custom ASIC Verification and FPGA Education Platform.
MSE 2003: 64-65 |
| 2002 |
|---|
| 20 | | Martin L. Leuschen,
Joseph R. Cavallaro,
Ian D. Walker:
Robotic Fault Detection using Nonlinear Analytical Redundancy.
ICRA 2002: 456-463 |
| 19 | EE | Yuanbin Guo,
Joseph R. Cavallaro:
Post-compensation of RF non-linearity in mobile OFDM systems by estimation of memory-less polynomial.
ISCAS (1) 2002: 217-220 |
| 18 | EE | Frank Livingston,
Vikram Chandrasekhar,
M. Vaya,
Joseph R. Cavallaro:
Handset detector architectures for DS-CDMA wireless systems.
ISCAS (3) 2002: 265-268 |
| 17 | EE | Yuanbin Guo,
Joseph R. Cavallaro:
A novel adaptive pre-distorter using LS estimation of SSPA non-linearity in mobile OFDM systems.
ISCAS (3) 2002: 453-456 |
| 16 | EE | Gang Xu,
Sridhar Rajagopal,
Joseph R. Cavallaro,
Behnaam Aazhang:
VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers.
VLSI Signal Processing 30(1-3): 21-33 (2002) |
| 15 | EE | Sridhar Rajagopal,
Srikrishna Bhashyam,
Joseph R. Cavallaro,
Behnaam Aazhang:
Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers.
VLSI Signal Processing 31(2): 143-156 (2002) |
| 2001 |
|---|
| 14 | EE | Sridhar Rajagopal,
Joseph R. Cavallaro:
On-line Arithmetic for Detection in Digital Communication Receivers.
IEEE Symposium on Computer Arithmetic 2001: 257-265 |
| 13 | EE | Sridhar Rajagopal,
Joseph R. Cavallaro:
A bit-streaming, pipelined multiuser detector for wireless communication receivers.
ISCAS (4) 2001: 128-131 |
| 2000 |
|---|
| 12 | EE | Sridhar Rajagopal,
Srikrishna Bhashyam,
Joseph R. Cavallaro,
Behnaam Aazhang:
Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers.
ASAP 2000: 173-184 |
| 1999 |
|---|
| 11 | | Ian D. Walker,
Joseph R. Cavallaro,
Martin L. Leuschen:
Keeping the Analog Genie in the Bottle: A Case for Digital Robots.
ICRA 1999: 1063-1070 |
| 1997 |
|---|
| 10 | EE | B. Haller,
J. Goetze,
Joseph R. Cavallaro:
Efficient Implementation of Rotation Operations for High Performance QRD-RLS Filtering.
ASAP 1997: 162- |
| 1994 |
|---|
| 9 | | M. L. Visinsky,
Ian D. Walker,
Joseph R. Cavallaro:
New Dynamic Model-Based Fault Detection Thresholds for Robot Manipulators.
ICRA 1994: 1388-1395 |
| 8 | | Nariankadu D. Hemkumar,
Joseph R. Cavallaro:
Redundant and On-Line CORDIC for Unitary Transformations.
IEEE Trans. Computers 43(8): 941-954 (1994) |
| 7 | EE | Ian D. Walker,
Joseph R. Cavallaro:
Parallel VLSI architectures for real-time kinematics of redundant robots.
Journal of Intelligent and Robotic Systems 9(1-2): 25-43 (1994) |
| 1993 |
|---|
| 6 | | Ian D. Walker,
Joseph R. Cavallaro:
Parallel VLSI Architectures for Real-Time Kinematics of Redundant Robots.
ICRA (1) 1993: 870-877 |
| 5 | | M. L. Visinsky,
Ian D. Walker,
Joseph R. Cavallaro:
Layered Dynamic Fault Detection and Tolerance for Robots.
ICRA (2) 1993: 180-187 |
| 4 | EE | Nariankadu D. Hemkumar,
Joseph R. Cavallaro:
Efficient complex matrix transformations with CORDIC.
IEEE Symposium on Computer Arithmetic 1993: 122-129 |
| 3 | | Kishore Kota,
Joseph R. Cavallaro:
Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors.
IEEE Trans. Computers 42(7): 769-779 (1993) |
| 1991 |
|---|
| 2 | | Arati S. Deo,
Joseph R. Cavallaro,
Ian D. Walker:
New Real-Time Robot Motion Algorithms Using Parallel VLSI Architectures.
PPSC 1991: 369-375 |
| 1988 |
|---|
| 1 | | Joseph R. Cavallaro,
Franklin T. Luk:
CORDIC Arithmetic for an SVD Processor.
J. Parallel Distrib. Comput. 5(3): 271-290 (1988) |
