| 2006 |
|---|
| 9 | EE | Ahmed M. Shams,
Archana Chidanandan,
Wendi Pan,
Magdy A. Bayoumi:
NEDA: a low-power high-performance DCT architecture.
IEEE Transactions on Signal Processing 54(3): 955-964 (2006) |
| 2004 |
|---|
| 8 | EE | Mohamed A. Elgamel,
Magdy A. Bayoumi,
Ahmed M. Shams,
Bertrand Zavidovique:
Low Power Full Search Block Matching Motion Estimation Vlsi Architectures.
Journal of Circuits, Systems, and Computers 13(6): 1271-1288 (2004) |
| 2002 |
|---|
| 7 | EE | Ahmed M. Shams,
Wendi Pan,
Archana Chidanandan,
Magdy A. Bayoumi:
A Low Power High Performance Distributed DCT Architecture.
ISVLSI 2002: 26-34 |
| 6 | EE | Ahmed M. Shams,
T. K. Darwish,
Magdy A. Bayoumi:
Performance analysis of low-power 1-bit CMOS full adder cells.
IEEE Trans. VLSI Syst. 10(1): 20-29 (2002) |
| 2001 |
|---|
| 5 | EE | Mohamed A. Elgamel,
Ahmed M. Shams,
Xi Xueling,
Magdy A. Bayoumi:
Enhanced low power motion estimation VLSI architectures for video compression.
ISCAS (4) 2001: 474-477 |
| 4 | EE | Ahmed M. Shams,
Mohamed A. Elgamel,
Magdy A. Bayoumi:
Hybrid Mesh-Based/Block-Based Motion Compensation Architecture.
Workshop on Digital and Computational Video 2001: 194-201 |
| 2000 |
|---|
| 3 | EE | Ahmed M. Shams,
Magdy A. Bayoumi:
A 108 Gbps, 1.5 GHz 1D-DCT Architecture.
ASAP 2000: 163-172 |
| 1999 |
|---|
| 2 | EE | Ahmed M. Shams,
Magdy A. Bayoumi:
Performance evaluation of 1-bit CMOS adder cells.
ISCAS (1) 1999: 27-30 |
| 1998 |
|---|
| 1 | EE | Ahmed M. Shams,
Magdy A. Bayoumi:
A New Full Adder Cell for Low-Power Applications.
Great Lakes Symposium on VLSI 1998: 45- |
