Chien-Hsiung Lee

2007
2	EE	Jyh-Ting Lai, An-Yeu Wu, Chien-Hsiung Lee: Joint AGC-Equalization Algorithm and VLSI Architecture for Wirelined Transceiver Designs. IEEE Trans. VLSI Syst. 15(2): 236-240 (2007)
2001
1	EE	Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu: A serial link transceiver for USB2 high-speed mode. ISCAS (4) 2001: 72-75

Coauthor Index

1	Jui-Ta Chiu	[1]
2	Shyh-Jye Jou	[1]
3	Chu King	[1]
4	Shu-Hua Kuo	[1]
5	Jyh-Ting Lai	[2]
6	Tim Liu	[1]
7	An-Yeu Wu	[2]