2008 |
13 | EE | Jim Harkin,
Fearghal Morgan,
Steve Hall,
Piotr Dudek,
Thomas Dowrick,
Liam McDaid:
Reconfigurable platforms and the challenges for large-scale implementations of spiking neural networks.
FPL 2008: 483-486 |
12 | EE | Alexey Lopich,
Piotr Dudek:
ASPA: Focal Plane digital processor array with asynchronous processing capabilities.
ISCAS 2008: 1592-1595 |
11 | EE | David López Vilariño,
Piotr Dudek,
Diego Cabello:
Focal-plane moving object segmentation for realtime video surveillance.
ISCAS 2008: 1600-1603 |
10 | EE | Jayawan H. B. Wijekoon,
Piotr Dudek:
Integrated circuit implementation of a cortical neuron.
ISCAS 2008: 1784-1787 |
9 | EE | Jayawan H. B. Wijekoon,
Piotr Dudek:
Compact silicon neuron circuit with spiking and bursting behaviour.
Neural Networks 21(2-3): 524-534 (2008) |
2007 |
8 | EE | Jayawan H. B. Wijekoon,
Piotr Dudek:
Spiking and Bursting Firing Patterns of a Compact VLSI Cortical Neuron Circuit.
IJCNN 2007: 1332-1337 |
7 | EE | David R. W. Barr,
Piotr Dudek,
Jonathan M. Chambers,
Kevin Gurney:
Implementation of multi-layer leaky integrator networks on a cellular processor array.
IJCNN 2007: 1560-1565 |
6 | EE | David López Vilariño,
Piotr Dudek:
Evolution of Pixel Level Snakes towards an efficient hardware implementation.
ISCAS 2007: 2678-2681 |
2006 |
5 | EE | Alexey Lopich,
Piotr Dudek:
Architecture of a VLSI cellular processor array for synchronous/asynchronous image processing.
ISCAS 2006 |
2005 |
4 | EE | Piotr Dudek:
Implementation of SIMD vision chip with 128×128 array of analogue processing elements.
ISCAS (6) 2005: 5806-5809 |
2004 |
3 | | Piotr Dudek:
A 39/spl times/48 general-purpose focal-plane processor array integrated circuit.
ISCAS (5) 2004: 448-452 |
2003 |
2 | EE | Piotr Dudek:
A flexible global readout architecture for an analogue SIMD vision chip.
ISCAS (3) 2003: 782-785 |
2001 |
1 | EE | Piotr Dudek,
P. J. Hicks:
An analogue SIMD focal-plane processor array.
ISCAS (4) 2001: 490-493 |