| |
| 2001 | ||
|---|---|---|
| 2 | EE | Ian Brynjolfson, Zeljko Zilic: A new PLL design for clock management applications. ISCAS (4) 2001: 814-817 |
| 2000 | ||
| 1 | EE | Ian Brynjolfson, Zeljko Zilic: FPGA clock management for low power applications (poster abstract). FPGA 2000: 219 |
| 1 | Zeljko Zilic | [1] [2] |