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Sridhar Rajagopal

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2008
8EESridhar Rajagopal, Joseph R. Cavallaro: Communication Processors for Wireless Systems. Wiley Encyclopedia of Computer Science and Engineering 2008
2006
7EESridhar Rajagopal, Joseph R. Cavallaro: Truncated Online Arithmetic with Applications to Communication Systems. IEEE Trans. Computers 55(10): 1240-12529 (2006)
2004
6EESridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner: Design Space Exploration for Real-Time Embedded Stream Processors. IEEE Micro 24(4): 54-66 (2004)
2002
5EEGang Xu, Sridhar Rajagopal, Joseph R. Cavallaro, Behnaam Aazhang: VLSI Implementation of the Multistage Detector for Next Generation Wideband CDMA Receivers. VLSI Signal Processing 30(1-3): 21-33 (2002)
4EESridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang: Efficient VLSI Architectures for Multiuser Channel Estimation in Wireless Base-Station Receivers. VLSI Signal Processing 31(2): 143-156 (2002)
2001
3EESridhar Rajagopal, Joseph R. Cavallaro: On-line Arithmetic for Detection in Digital Communication Receivers. IEEE Symposium on Computer Arithmetic 2001: 257-265
2EESridhar Rajagopal, Joseph R. Cavallaro: A bit-streaming, pipelined multiuser detector for wireless communication receivers. ISCAS (4) 2001: 128-131
2000
1EESridhar Rajagopal, Srikrishna Bhashyam, Joseph R. Cavallaro, Behnaam Aazhang: Efficient VLSI Architectures for Baseband Signal Processing in Wireless Base-Station Receivers. ASAP 2000: 173-184

Coauthor Index

1Behnaam Aazhang [1] [4] [5]
2Srikrishna Bhashyam [1] [4]
3Joseph R. Cavallaro [1] [2] [3] [4] [5] [6] [7] [8]
4Scott Rixner [6]
5Gang Xu [5]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)