Yngvar Berg

2008
35	EE	Omid Mirmotahari, Yngvar Berg: Proposal for a Bidirectional Gate Using Pseudo Floating-Gate. DELTA 2008: 196-200
34	EE	Omid Mirmotahari, Yngvar Berg: Low Voltage Design against Power Analysis Attacks. DELTA 2008: 545-548
33	EE	Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet: High Speed Ultra Low Voltage CMOS inverter. ISVLSI 2008: 122-127
32	EE	Omid Mirmotahari, Yngvar Berg: Ultra Low Voltage High Speed Differential CMOS Inverter. PATMOS 2008: 328-337
2007
31	EE	Henning Gundersen, Yngvar Berg: Fast Addition Using Balanced Ternary Counters Designed with CMOS Semi-Floating Gate Devices. ISMVL 2007: 30
30	EE	Renè Jensen, Yngvar Berg: Dual Data-Rate Cyclic D/A Converter Using Semi Floating-Gate Devices. ISMVL 2007: 37
29	EE	Yngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet: Fault Tolerant CMOS Logic Using Ternary Gates. ISMVL 2007: 38
2006
28		Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg: Multiple Valued Counter. DDECS 2006: 247-249
27		Johannes Goplen Lomsdalen, Renè Jensen, Yngvar Berg: Self-refreshing Multiple Valued Memory. DDECS 2006: 94-96
26	EE	Henning Gundersen, Yngvar Berg: A novel ternary more, less and equality circuit using recharged semi-floating gate devices. ISCAS 2006
25	EE	Øivind Næss, Yngvar Berg: Switched pseudo floating-gate reconfigurable linear threshold elements. ISCAS 2006
24	EE	Henning Gundersen, Yngvar Berg: A Novel Balanced Ternary Adder Using Recharged Semi-Floating Gate Devices. ISMVL 2006: 18
23	EE	Yngvar Berg, Omid Mirmotahari, Snorre Aunet: Pseudo Floating-Gate Inverter with Feedback Control. VLSI-SoC 2006: 272-277
2005
22	EE	Henning Gundersen, Renè Jensen, Yngvar Berg: A Novel Ternary Switching Element Using CMOS Recharge Semi Floating-Gate Devices. ISMVL 2005: 54-58
2004
21		Henning Gundersen, Yngvar Berg: Max and min functions using Multiple-Valued Recharged Semi-Floating Gate circuits. ISCAS (2) 2004: 857-860
20	EE	Omid Mirmotahari, Yngvar Berg: A Systolic Parallel Multiplier over GF(3m) Using Neuron-MOS DLC. ISMVL 2004: 135-138
19	EE	Omid Mirmotahari, Yngvar Berg: A Novel D-Latch in Multiple-Valued Semi-Floating-Gate Recharged Logic. ISMVL 2004: 210-213
18	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari: Basic Multiple-Valued Functions Using Recharge CMOS Logic. ISMVL 2004: 346-351
2003
17	EE	Øivind Næss, Espen A. Olsen, Yngvar Berg, Tor Sverre Lande: A low voltage second order biquad using pseudo floating-gate transistors. ISCAS (1) 2003: 125-128
16	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin: Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. ISCAS (1) 2003: 345-348
15	EE	Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin: Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. ISCAS (5) 2003: 193-196
14	EE	Omid Mirmotahari, Yngvar Berg: A Novel Multiple-Input Multiple-Valued Semi-Floating-Gate LATC. ISMVL 2003: 227-
13	EE	Snorre Aunet, Yngvar Berg: UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3". IWANN (2) 2003: 57-64
2002
12	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin: A novel floating-gate multiple-valued CMOS full-adder. ISCAS (1) 2002: 877-880
11	EE	Øivind Næss, Yngvar Berg: Tunable floating-gate low-voltage transconductor. ISCAS (4) 2002: 663-666
10	EE	Yngvar Berg, Øivind Næss, Snorre Aunet, Renè Jensen, Mats Høvin: Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. ISCAS (5) 2002: 385-388
9	EE	Mats Høvin, Dag T. Wisland, Yngvar Berg, Tor Sverre Lande: A low-voltage sinc/sup 2/ decimator implemented by a new circuit technique using floating-gate MOS transistors. ISCAS (5) 2002: 397-400
8	EE	Johannes Goplen Lomsdalen, Yngvar Berg, Renè Jensen: A low-voltage floating-gate CMOS transconductance amplifier, and a spin-off quasi frequency tripler. ISCAS (5) 2002: 501-504
7	EE	Mats Høvin, Dag T. Wisland, Yngvar Berg, J. T. Marienborg, Tor Sverre Lande: Delta-sigma modulation in single neurons. ISCAS (5) 2002: 617-620
2001
6	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin: Extreme low-voltage floating-gate CMOS transconductance amplifier. ISCAS (1) 2001: 37-40
5	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin: Floating-gate CMOS differential analog inverter for ultra low-voltage applications. ISCAS (1) 2001: 9-12
4	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin: Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. ISCAS (4) 2001: 838-841
1999
3	EE	Yngvar Berg, Tor Sverre Lande: Tunable current mirrors for ultra low voltage. ISCAS (2) 1999: 17-20
2	EE	Yngvar Berg, Tor Sverre Lande: Area efficient circuit tuning with floating-gate techniques. ISCAS (2) 1999: 396-399
1995
1		Yngvar Berg, Jon-Erik Ruth, Tor Sverre Lande: Scalable Mean Rate Signal Encoding Analog Neural Network. ISCAS 1995: 1668-1671

Coauthor Index

1	Snorre Aunet	[4] [5] [6] [10] [12] [13] [15] [16] [18] [23] [29] [33]
2	Henning Gundersen	[6] [21] [22] [24] [26] [29] [31]
3	O. Hagen	[12]
4	Mats Erling Høvin (Mats Høvin)	[4] [5] [6] [7] [9] [10] [12] [15] [16]
5	Renè Jensen	[8] [10] [22] [27] [28] [29] [30]
6	Tor Sverre Lande	[1] [2] [3] [7] [9] [17]
7	Johannes Goplen Lomsdalen	[8] [16] [27] [28] [29] [33]
8	J. T. Marienborg	[7]
9	Omid Mirmotahari	[14] [15] [18] [19] [20] [23] [32] [33] [34] [35]
10	Øivind Næss	[4] [5] [6] [10] [11] [12] [16] [17] [18] [25]
11	Espen A. Olsen	[17]
12	Jon-Erik Ruth	[1]
13	Dag T. Wisland	[7] [9]