| 2008 |
|---|
| 19 | EE | Gian-Carlo Cardarilli,
Luca Di Nunzio,
Marco Re,
Alberto Nannarelli:
ADAPTO: full-adder based reconfigurable architecture for bit level operations.
ISCAS 2008: 3434-3437 |
| 2007 |
|---|
| 18 | EE | G. L. Bernocchi,
Gian-Carlo Cardarilli,
Andrea Del Re,
Alberto Nannarelli,
Marco Re:
Low-power adaptive filter based on RNS components.
ISCAS 2007: 3211-3214 |
| 17 | EE | Tomás Lang,
Alberto Nannarelli:
A Radix-10 Digit-Recurrence Division Unit: Algorithm and Architecture.
IEEE Trans. Computers 56(6): 727-739 (2007) |
| 2005 |
|---|
| 16 | EE | Elisardo Antelo,
Tomás Lang,
Paolo Montuschi,
Alberto Nannarelli:
Low Latency Digit-Recurrence Reciprocal and Square-Root Reciprocal Algorithm and Architecture.
IEEE Symposium on Computer Arithmetic 2005: 147-154 |
| 15 | EE | Gian-Carlo Cardarilli,
Andrea Del Re,
Alberto Nannarelli,
Marco Re:
Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter.
ISCAS (2) 2005: 1102-1105 |
| 14 | EE | Elisardo Antelo,
Tomás Lang,
Paolo Montuschi,
Alberto Nannarelli:
Digit-Recurrence Dividers with Reduced Logical Depth.
IEEE Trans. Computers 54(7): 837-851 (2005) |
| 2004 |
|---|
| 13 | EE | Andrea Del Re,
Alberto Nannarelli,
Marco Re:
A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters.
DATE 2004: 686-687 |
| 12 | | Gian-Carlo Cardarilli,
Andrea Del Re,
Alberto Nannarelli,
Marco Re:
Low-power implementation of polyphase filters in Quadratic Residue Number system.
ISCAS (2) 2004: 725-728 |
| 2003 |
|---|
| 11 | EE | Alberto Nannarelli,
Gian-Carlo Cardarilli,
Marco Re:
Power-delay tradeoffs in residue number system.
ISCAS (5) 2003: 413-416 |
| 2002 |
|---|
| 10 | EE | Elisardo Antelo,
Tomás Lang,
Paolo Montuschi,
Alberto Nannarelli:
Fast Radix-4 Retimed Division with Selection by Comparisons.
ASAP 2002: 185-196 |
| 9 | EE | Gian-Carlo Cardarilli,
Andrea Del Re,
Alberto Nannarelli,
Marco Re:
Power characterization of digital filters implemented on FPGA.
ISCAS (5) 2002: 801-804 |
| 2001 |
|---|
| 8 | EE | Alberto Nannarelli,
Marco Re,
Gian-Carlo Cardarilli:
Tradeoffs between residue number system and traditional FIR filters.
ISCAS (2) 2001: 305-308 |
| 7 | EE | Marco Re,
Alberto Nannarelli,
Gian-Carlo Cardarilli,
Roberto Lojacono:
FPGA realization of RNS to binary signed conversion architecture.
ISCAS (4) 2001: 350-353 |
| 6 | EE | Luca Benini,
Alberto Macii,
Alberto Nannarelli:
Cached-code compression for energy minimization in embedded processors.
ISLPED 2001: 322-327 |
| 1999 |
|---|
| 5 | EE | Alberto Nannarelli,
Tomás Lang:
Low-Power Radix-4 Combined Division and Square Root.
ICCD 1999: 236-242 |
| 4 | EE | Alberto Nannarelli,
Tomás Lang:
Low-Power Division: Comparison among Implementations of Radix 4, 8 and 16.
IEEE Symposium on Computer Arithmetic 1999: 60- |
| 3 | EE | Alberto Nannarelli,
Tomás Lang:
Low-Power Divider.
IEEE Trans. Computers 48(1): 2-14 (1999) |
| 1998 |
|---|
| 2 | EE | Alberto Nannarelli,
Tomás Lang:
Power-delay tradeoffs for radix-4 and radix-8 dividers.
ISLPED 1998: 109-111 |
| 1996 |
|---|
| 1 | EE | Alberto Nannarelli,
Tomás Lang:
Low-power radix-4 divider.
ISLPED 1996: 205-208 |
