| 2008 |
|---|
| 6 | EE | Koichi Hamamoto,
Hiroshi Fuketa,
Masanori Hashimoto,
Yukio Mitsuyama,
Takao Onoye:
Experimental study on body-biasing layout style-- negligible area overhead enables sufficient speed controllability --.
ACM Great Lakes Symposium on VLSI 2008: 387-390 |
| 5 | EE | Hiroshi Fuketa,
Masanori Hashimoto,
Yukio Mitsuyama,
Takao Onoye:
Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits.
ISLPED 2008: 3-8 |
| 2005 |
|---|
| 4 | EE | Yukio Mitsuyama,
Motoki Kimura,
Takao Onoye,
Isao Shirakawa:
Architecture of IEEE802.11i Cipher Algorithms for Embedded Systems.
IEICE Transactions 88-A(4): 899-906 (2005) |
| 2001 |
|---|
| 3 | EE | Yukio Mitsuyama,
Zaldy Andales,
Takao Onoye,
Isao Shirakawa:
A dynamically reconfigurable hardware-based cipher chip.
ASP-DAC 2001: 11-12 |
| 2 | EE | Yukio Mitsuyama,
Zaldy Andales,
Takao Onoye,
Isao Shirakawa:
VLSI architecture of dynamically reconfigurable hardware-based cipher.
ISCAS (4) 2001: 734-737 |
| 1999 |
|---|
| 1 | EE | Koji Asari,
Yukio Mitsuyama,
Takao Onoye,
Isao Shirakawa,
Hiroshige Hirano,
Toshiyuki Honda,
Tatsuo Otsuki,
Takaaki Baba,
Teresa H. Y. Meng:
FeRAM Circuit Technology for System on a Chip.
Evolvable Hardware 1999: 193- |
