| 2007 |
|---|
| 11 | EE | Boyan Semerdjiev,
Dimitrios Velenis:
Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect Trees.
ISCAS 2007: 1125-1128 |
| 10 | EE | Boyan Semerdjiev,
Dimitrios Velenis:
Optimal Crosstalk Shielding Insertion along On-Chip Interconnect Trees.
VLSI Design 2007: 289-294 |
| 2006 |
|---|
| 9 | EE | William R. Roberts,
Dimitrios Velenis:
Effects of process and environmental variations on timing characteristics of clocked registers.
ACM Great Lakes Symposium on VLSI 2006: 165-168 |
| 8 | EE | Itisha Chanodia,
Dimitrios Velenis:
Effects of crosstalk noise on H-tree clock distribution networks.
ISCAS 2006 |
| 7 | EE | William R. Roberts,
Dimitrios Velenis:
Power supply variation effects on timing characteristics of clocked registers.
ISCAS 2006 |
| 6 | EE | Itisha Chanodia,
Dimitrios Velenis:
Effects of Parameter Variations and Crosstalk Noise on H-Tree Clock Distribution Networks.
ISVLSI 2006: 456-457 |
| 2005 |
|---|
| 5 | EE | William R. Roberts,
Dimitrios Velenis:
Parameter Variation Effects on Timing Characteristics of High Performance Clocked Registers.
PATMOS 2005: 508-517 |
| 2004 |
|---|
| 4 | EE | Dimitrios Velenis,
Eby G. Friedman:
Buffer Sizing for Crosstalk Induced Delay Uncertainty.
PATMOS 2004: 750-759 |
| 2003 |
|---|
| 3 | EE | Dimitrios Velenis,
Marios C. Papaefthymiou,
Eby G. Friedman:
Reduced Delay Uncertainty in High Performance Clock Distribution Networks.
DATE 2003: 10068-10075 |
| 2002 |
|---|
| 2 | EE | Dimitrios Velenis,
Kevin T. Tang,
Ivan S. Kourtev,
V. Adler,
F. Baez,
Eby G. Friedman:
Demonstration of Speed and Power Enhancements on an Industrial Circuit Through Application of Clock Skew Scheduling.
Journal of Circuits, Systems, and Computers 11(3): 231-246 (2002) |
| 2001 |
|---|
| 1 | EE | Dimitrios Velenis,
Eby G. Friedman,
Marios C. Papaefthymiou:
A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty.
ISCAS (4) 2001: 422-425 |
