| 2008 |
|---|
| 7 | EE | Kuo-Hsing Cheng,
Cheng-Liang Hung,
Chih-Hsien Chang,
Yu-lung Lo,
Wei-Bin Yang,
Jiunn-Way Miaw:
A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III.
DDECS 2008: 64-67 |
| 2007 |
|---|
| 6 | EE | Chung-Yu Chang,
Wei-Bin Yang,
Ching-Ji Huang,
Cheng-Hsing Chien:
New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode.
ISCAS 2007: 3740-3743 |
| 2006 |
|---|
| 5 | EE | Ting-Sheng Jau,
Wei-Bin Yang,
Chung-Yu Chang:
Analysis and Design of High Performance, Low Power Multiple Ports Register Files.
APCCAS 2006: 1453-1456 |
| 4 | EE | Shu-Chang Kuo,
Tzu-Chien Hung,
Wei-Bin Yang:
The new improved pseudo fractional-N clock generator with 50% duty cycle.
ISCAS 2006 |
| 2005 |
|---|
| 3 | EE | Kuo-Hsing Cheng,
Shu-Ming Chang,
Shu-Yu Jiang,
Wei-Bin Yang:
A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit.
ISCAS (2) 2005: 1174-1177 |
| 2004 |
|---|
| 2 | EE | Kuo-Hsing Cheng,
Wei-Bin Yang,
Shu-Chang Kuo:
A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.
ISCAS (1) 2004: 777-780 |
| 2001 |
|---|
| 1 | EE | Kuo-Hsing Cheng,
Wei-Bin Yang,
Chun-Fu Chung:
A low-power high driving ability voltage control oscillator used in PLL.
ISCAS (4) 2001: 614-617 |
