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Wei-Bin Yang

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2008
7EEKuo-Hsing Cheng, Cheng-Liang Hung, Chih-Hsien Chang, Yu-lung Lo, Wei-Bin Yang, Jiunn-Way Miaw: A Spread-Spectrum Clock Generator Using Fractional PLL Controlled Delta-Sigma Modulator for Serial-ATA III. DDECS 2008: 64-67
2007
6EEChung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien: New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition Mode. ISCAS 2007: 3740-3743
2006
5EETing-Sheng Jau, Wei-Bin Yang, Chung-Yu Chang: Analysis and Design of High Performance, Low Power Multiple Ports Register Files. APCCAS 2006: 1453-1456
4EEShu-Chang Kuo, Tzu-Chien Hung, Wei-Bin Yang: The new improved pseudo fractional-N clock generator with 50% duty cycle. ISCAS 2006
2005
3EEKuo-Hsing Cheng, Shu-Ming Chang, Shu-Yu Jiang, Wei-Bin Yang: A 2GHz fully differential DLL-based frequency multiplier for high speed serial link circuit. ISCAS (2) 2005: 1174-1177
2004
2EEKuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo: A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. ISCAS (1) 2004: 777-780
2001
1EEKuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung: A low-power high driving ability voltage control oscillator used in PLL. ISCAS (4) 2001: 614-617

Coauthor Index

1Chih-Hsien Chang [7]
2Chung-Yu Chang [5] [6]
3Shu-Ming Chang [3]
4Kuo-Hsing Cheng [1] [2] [3] [7]
5Cheng-Hsing Chien [6]
6Chun-Fu Chung [1]
7Ching-Ji Huang [6]
8Cheng-Liang Hung [7]
9Tzu-Chien Hung [4]
10Ting-Sheng Jau [5]
11Shu-Yu Jiang [3]
12Shu-Chang Kuo [2] [4]
13Yu-lung Lo [7]
14Jiunn-Way Miaw [7]

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)