2008 |
18 | EE | Tzai-Zang Lee,
Chien-Hsing Wu,
Hsien-Hui Wei:
KBSLUA: A knowledge-based system applied in river land use assessment.
Expert Syst. Appl. 34(2): 889-899 (2008) |
2005 |
17 | EE | Chien-Hsing Wu,
Yan-Chr Tsai,
Hwa-Long Tsai:
Quantum circuits for stabilizer codes.
ISCAS (3) 2005: 2333-2336 |
16 | EE | Chien-Hsing Wu,
Shu-Chen Kao,
Yann-Yean Su,
Chuan-Chun Wu:
Targeting customers via discovery knowledge for the insurance industry.
Expert Syst. Appl. 29(2): 291-299 (2005) |
15 | EE | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Yin-Tsung Hwang,
Jun-Hong Chen:
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. VLSI Syst. 13(4): 439-447 (2005) |
2004 |
14 | | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Yin-Tsung Hwang,
Jun-Hong Chen,
Hsin-Fu Lo:
VLSI architecture exploration for sliding-window Log-MAP decoders.
ISCAS (2) 2004: 513-516 |
13 | EE | Chien-Hsing Wu:
Building knowledge structures for online instructional/learning systems via knowledge elements interrelations.
Expert Syst. Appl. 26(3): 311-319 (2004) |
12 | EE | Chien-Hsing Wu,
Chien-Ming Wu,
Ming-Der Shieh,
Yin-Tsung Hwang:
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
IEEE Trans. Computers 53(3): 375-380 (2004) |
11 | EE | Chien-Hsing Wu,
Tzai-Zang Lee,
Shu-Chen Kao:
Knowledge discovery applied to material acquisitions for libraries.
Inf. Process. Manage. 40(4): 709-725 (2004) |
2003 |
10 | EE | Yin-Tsung Hwang,
Kuo-Wei Liao,
Chien-Hsing Wu:
FPGA realization of an OFDM frame synchronization design for dispersive channels.
ISCAS (2) 2003: 256-259 |
9 | EE | Chien-Hsing Wu:
Data mining applied to material acquisition budget allocation for libraries: design and development.
Expert Syst. Appl. 25(3): 401-411 (2003) |
2002 |
8 | EE | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu:
Memory arrangements in turbo decoders using sliding-window BCJR algorithm.
ISCAS (5) 2002: 557-560 |
7 | EE | Chien-Hsing Wu,
Chien-Ming Wu,
Ming-Der Shieh,
Yin-Tsung Hwang:
An area-efficient systolic division circuit over GF(2/sup m/) for secure communication.
ISCAS (5) 2002: 733-736 |
6 | EE | Chien-Hsing Wu:
SODPM: a sequence-oriented decision process model for unstructured group decision problems.
Behaviour & IT 21(1): 59-69 (2002) |
5 | EE | Chien-Hsing Wu,
Shu-Chen Kao:
Induction-based approach to rule generation using membership function.
Int. J. Computer Integrated Manufacturing 15(1): 86-96 (2002) |
2001 |
4 | EE | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Ming-Hwa Sheu:
VLSI architecture of extended in-place path metric update for Viterbi decoders.
ISCAS (4) 2001: 206-209 |
3 | EE | Chien-Hsing Wu,
Chien-Ming Wu,
Ming-Der Shieh,
Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
ISCAS (4) 2001: 33-36 |
1999 |
2 | EE | Che-Han Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Ming-Hwa Sheu,
Jia-Lin Sheu:
A VLSI architecture of fast high-radix modular multiplication for RSA cryptosystem.
ISCAS (1) 1999: 500-503 |
1 | EE | Jin-Chuan Huang,
Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu:
An area-efficient versatile Reed-Solomon decoder for ADSL.
ISCAS (1) 1999: 517-520 |