Chien-Ming Wu

2008
17	EE	Chun-Ming Huang, Chien-Ming Wu, Chih-Chyau Yang, Chin-Long Wey: PrSoC: Programmable System-on-chip (SoC) for silicon prototyping. ISCAS 2008: 3382-3385
16	EE	Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu: Reducing Interconnect Complexity for Efficient Path Metric Memory Management in Viterbi Decoders. IEICE Transactions 91-D(9): 2300-2311 (2008)
2006
15	EE	Ming-Der Shieh, Tai-Ping Wang, Chien-Ming Wu, Chun-Ming Huang: Efficient path metric access for reducing interconnect overhead in Viterbi decoders. ISCAS 2006
14	EE	Ming-Der Shieh, Jun-Hong Chen, Chien-Ming Wu: High-Speed Design of Montgomery Inverse Algorithm over GF(2m). IEICE Transactions 89-A(2): 559-565 (2006)
2005
13	EE	Hong-Yu Chao, Jia-Shung Wang, Juin-Long Lin, Kai-Chao Yang, Chien-Ming Wu, Chun-Ming Huang, Lan-Da Van: High-performance low-complexity bit-plane coding scheme for MPEG-4 FGS. ICME 2005: 89-92
12	EE	Jun-Hong Chen, Ming-Der Shieh, Chien-Ming Wu: Concurrent algorithm for high-speed point multiplication in elliptic curve cryptography. ISCAS (5) 2005: 5254-5257
11	EE	Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen: VLSI architectural design tradeoffs for sliding-window log-MAP decoders. IEEE Trans. VLSI Syst. 13(4): 439-447 (2005)
2004
10		Lan-Da Van, Hsin-Fu Luo, Chien-Ming Wu, Wen-Hsiang Hu, Chun-Ming Huang, Wei-Chang Tsai: A high-performance area-aware DSP processor architecture for video codecs. ICME 2004: 1499-1502
9		Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Yin-Tsung Hwang, Jun-Hong Chen, Hsin-Fu Lo: VLSI architecture exploration for sliding-window Log-MAP decoders. ISCAS (2) 2004: 513-516
8	EE	Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m). IEEE Trans. Computers 53(3): 375-380 (2004)
2003
7	EE	Chien-Ming Wu, Ming-Der Shieh, Hsin-Fu Lo, Min-Hsiung Hu: Implementation of channel demodulator for DAB system. ISCAS (2) 2003: 137-140
2002
6	EE	Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu: Memory arrangements in turbo decoders using sliding-window BCJR algorithm. ISCAS (5) 2002: 557-560
5	EE	Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: An area-efficient systolic division circuit over GF(2/sup m/) for secure communication. ISCAS (5) 2002: 733-736
2001
4	EE	Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu: VLSI architecture of extended in-place path metric update for Viterbi decoders. ISCAS (4) 2001: 206-209
3	EE	Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang: Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. ISCAS (4) 2001: 33-36
2	EE	Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu: Design of an efficient FFT processor for DAB system. ISCAS (4) 2001: 654-657
1999
1	EE	Jin-Chuan Huang, Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu: An area-efficient versatile Reed-Solomon decoder for ADSL. ISCAS (1) 1999: 517-520

Coauthor Index

1	Hong-Yu Chao	[13]
2	Jun-Hong Chen	[9] [11] [12] [14]
3	Min-Hsiung Hu	[7]
4	Wen-Hsiang Hu	[10]
5	Chun-Ming Huang	[10] [13] [15] [17]
6	Jin-Chuan Huang	[1]
7	Yin-Tsung Hwang	[3] [5] [8] [9] [11]
8	Juin-Long Lin	[13]
9	Hsin-Fu Lo	[2] [7] [9]
10	Hsin-Fu Luo	[10]
11	Ming-Hwa Sheu	[4]
12	Ming-Der Shieh	[1] [2] [3] [4] [5] [6] [7] [8] [9] [11] [12] [14] [15] [16]
13	Wei-Chang Tsai	[10]
14	Lan-Da Van	[10] [13]
15	Jia-Shung Wang	[13]
16	Tai-Ping Wang	[15] [16]
17	Chin-Long Wey	[17]
18	Chien-Hsing Wu	[1] [3] [4] [5] [6] [8] [9] [11]
19	Chih-Chyau Yang	[17]
20	Kai-Chao Yang	[13]