| 2008 |
|---|
| 13 | EE | Yeong-Kang Lai,
Lien-Fei Chen,
Tian-En Hsieh,
Shien-Yu Huang:
Hybrid parallel motion estimation architecture based on fast Pel-subsampling algorithm.
ICME 2008: 1021-1024 |
| 12 | EE | Lien-Fei Chen,
Kun-Hsing Li,
Chong-Yu Huang,
Yeong-Kang Lai:
Analysis and architecture design of multi-transform architecture for H.264/AVC intra frame coder.
ICME 2008: 145-148 |
| 11 | EE | Chong-Yu Huang,
Lien-Fei Chen,
Yeong-Kang Lai:
A high-speed 2-D transform architecture with unique kernel for multi-standard video applications.
ISCAS 2008: 21-24 |
| 2006 |
|---|
| 10 | EE | Yeong-Kang Lai,
Lien-Fei Chen,
Jian-Chou Chen,
Chun-Wei Chiu:
A Cost Effective Interconnection Network for Reconfigurable Computing Processor in Digital Signal Processing Applications.
IEICE Transactions 89-C(11): 1674-1675 (2006) |
| 2005 |
|---|
| 9 | EE | Yeong-Kang Lai,
Chih-Chung Chou,
Yu-Chieh Chung:
A simple and cost effective video encoder with memory-reducing CAVLC.
ISCAS (1) 2005: 432-435 |
| 8 | EE | Yeong-Kang Lai,
Lien-Fei Chen,
Jian-Chou Chen,
Chun-Wei Chiu:
A two-way SIMD-based reconfigurable computing architecture for multimedia applications.
ISCAS (5) 2005: 4578-4581 |
| 2004 |
|---|
| 7 | | Yeong-Kang Lai,
Lien-Fei Chen:
A performance-driven configurable motion estimator for full-search block-matching algorithm.
ISCAS (2) 2004: 233-236 |
| 6 | | Lien-Fei Chen,
Yeong-Kang Lai:
VLSI architecture of the reconfigurable computing engine for digital signal processing applications.
ISCAS (2) 2004: 937-940 |
| 5 | | Yeong-Kang Lai,
Li-Chung Chang,
Lien-Fei Chen,
Chi-Chung Chou,
Chun-Wei Chiu:
A novel memoryless AES cipher architecture for networking applications.
ISCAS (4) 2004: 333-336 |
| 2003 |
|---|
| 4 | EE | Yeong-Kang Lai,
Han-Jen Hsu:
A cost-effective 2-D discrete cosine transform processor with reconfigurable datapath.
ISCAS (2) 2003: 492-495 |
| 3 | EE | Yeong-Kang Lai,
Lien-Fei Chen:
A high data-reuse architecture with double-slice processing for full-search block-matching algorithm.
ISCAS (2) 2003: 716-719 |
| 2001 |
|---|
| 2 | EE | Yeong-Kang Lai,
Yu-Chuan Shu:
VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation.
ISCAS (4) 2001: 57-60 |
| 1997 |
|---|
| 1 | EE | Yeong-Kang Lai,
Liang-Gee Chen,
Yung-Pin Lee:
A flexible data-interlacing architecture for full-search block-matching algorithm.
ASAP 1997: 96- |
