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Snorre Aunet

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2009
28EEFarshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao: New subthreshold concepts in 65nm CMOS technology. ISQED 2009: 162-166
2008
27EEHåvard Pedersen Alstad, Snorre Aunet: Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. DDECS 2008: 12-13
26EEHåvard Pedersen Alstad, Snorre Aunet: Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology. DDECS 2008: 8-11
25EEYngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet: High Speed Ultra Low Voltage CMOS inverter. ISVLSI 2008: 122-127
24EEFarshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao: 65NM sub-threshold 11T-SRAM for ultra low voltage applications. SoCC 2008: 113-118
23EEKristian Granhaug, Snorre Aunet: Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. J. Electronic Testing 24(1-3): 157-163 (2008)
2007
22EEYngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet: Fault Tolerant CMOS Logic Using Ternary Gates. ISMVL 2007: 38
21EESnorre Aunet, Hans Kristian Otnes Berge: Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits. IWANN 2007: 455-462
20EEJon Alfredsson, Snorre Aunet: Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. PATMOS 2007: 536-545
19EEJon Alfredsson, Snorre Aunet, Bengt Oelmann: Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure. VLSI Design 2007: 314-317
2006
18 Kristian Granhaug, Snorre Aunet: Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. DDECS 2006: 27-32
17EEKristian Granhaug, Snorre Aunet: Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. DFT 2006: 20-28
16EEKristian Granhaug, Snorre Aunet, Tor Sverre Lande: Body-bias regulator for ultra low power multifunction CMOS gates. ISCAS 2006
15EEYngvar Berg, Omid Mirmotahari, Snorre Aunet: Pseudo Floating-Gate Inverter with Feedback Control. VLSI-SoC 2006: 272-277
2005
14EEValeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal: On the Advantages of Serial Architectures for Low-Power Reliable Computations. ASAP 2005: 276-281
13EEValeriu Beiu, Artur Zawadski, Razvan Andonie, Snorre Aunet: Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. IWANN 2005: 438-445
12EEValeriu Beiu, Asbjørn Djupdal, Snorre Aunet: Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. IWANN 2005: 486-493
2004
11EEYngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari: Basic Multiple-Valued Functions Using Recharge CMOS Logic. ISMVL 2004: 346-351
2003
10EESnorre Aunet, Morten Hartmann: Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware. ICES 2003: 365-376
9EEYngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin: Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. ISCAS (1) 2003: 345-348
8EEYngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin: Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. ISCAS (5) 2003: 193-196
7EESnorre Aunet, Yngvar Berg: UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3". IWANN (2) 2003: 57-64
2002
6EEYngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin: A novel floating-gate multiple-valued CMOS full-adder. ISCAS (1) 2002: 877-880
5EEYngvar Berg, Øivind Næss, Snorre Aunet, Renè Jensen, Mats Høvin: Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. ISCAS (5) 2002: 385-388
4EETrond Ytterdal, Snorre Aunet: Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. ISCAS (5) 2002: 393-396
2001
3EEYngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin: Extreme low-voltage floating-gate CMOS transconductance amplifier. ISCAS (1) 2001: 37-40
2EEYngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin: Floating-gate CMOS differential analog inverter for ultra low-voltage applications. ISCAS (1) 2001: 9-12
1EEYngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin: Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. ISCAS (4) 2001: 838-841

Coauthor Index

1Jon Alfredsson [19] [20]
2Håvard Pedersen Alstad [26] [27]
3Razvan Andonie [13]
4Valeriu Beiu [12] [13] [14]
5Yngvar Berg [1] [2] [3] [5] [6] [7] [8] [9] [11] [15] [22] [25]
6Hans Kristian Otnes Berge [21]
7Tuan Vu Cao [24] [28]
8Asbjørn Djupdal [12] [14]
9Kristian Granhaug [16] [17] [18] [23]
10Henning Gundersen [3] [22]
11O. Hagen [6]
12Morten Hartmann [10]
13Mats Erling Høvin (Mats Høvin) [1] [2] [3] [5] [6] [8] [9]
14Renè Jensen [5] [22]
15Tor Sverre Lande [16]
16Johannes Goplen Lomsdalen [9] [22] [25]
17Hamid Mahmoodi (Hamid Mahmoodi-Meimand) [24] [28]
18Omid Mirmotahari [8] [11] [15] [25]
19Farshad Moradi [24] [28]
20Øivind Næss [1] [2] [3] [5] [6] [9] [11]
21Jabulani Nyathi [14]
22Bengt Oelmann [19]
23Ali Peiravi [28]
24Ray Robert Rydberg III [14]
25Dag T. Wisland [24] [28]
26Trond Ytterdal [4]
27Artur Zawadski [13]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)