Snorre Aunet

2009
28	EE	Farshad Moradi, Dag T. Wisland, Hamid Mahmoodi, Ali Peiravi, Snorre Aunet, Tuan Vu Cao: New subthreshold concepts in 65nm CMOS technology. ISQED 2009: 162-166
2008
27	EE	Håvard Pedersen Alstad, Snorre Aunet: Improving Circuit Security against Power Analysis Attacks with Subthreshold Operation. DDECS 2008: 12-13
26	EE	Håvard Pedersen Alstad, Snorre Aunet: Three Subthreshold Flip-Flop Cells Characterized in 90 nm and 65 nm CMOS Technology. DDECS 2008: 8-11
25	EE	Yngvar Berg, Omid Mirmotahari, Johannes Goplen Lomsdalen, Snorre Aunet: High Speed Ultra Low Voltage CMOS inverter. ISVLSI 2008: 122-127
24	EE	Farshad Moradi, Dag T. Wisland, Snorre Aunet, Hamid Mahmoodi, Tuan Vu Cao: 65NM sub-threshold 11T-SRAM for ultra low voltage applications. SoCC 2008: 113-118
23	EE	Kristian Granhaug, Snorre Aunet: Improving Yield and Defect Tolerance in Subthreshold CMOS Through Output-Wired Redundancy. J. Electronic Testing 24(1-3): 157-163 (2008)
2007
22	EE	Yngvar Berg, Renè Jensen, Johannes Goplen Lomsdalen, Henning Gundersen, Snorre Aunet: Fault Tolerant CMOS Logic Using Ternary Gates. ISMVL 2007: 38
21	EE	Snorre Aunet, Hans Kristian Otnes Berge: Statistical Simulations for Exploring Defect Tolerance and Power Consumption for 4 Subthreshold 1-Bit Addition Circuits. IWANN 2007: 455-462
20	EE	Jon Alfredsson, Snorre Aunet: Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply. PATMOS 2007: 536-545
19	EE	Jon Alfredsson, Snorre Aunet, Bengt Oelmann: Small Fan-in Floating-Gate Circuits with Application to an Improved Adder Structure. VLSI Design 2007: 314-317
2006
18		Kristian Granhaug, Snorre Aunet: Six Subthreshold Full Adder Cells Characterized in 90 nm CMOS Technology. DDECS 2006: 27-32
17	EE	Kristian Granhaug, Snorre Aunet: Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. DFT 2006: 20-28
16	EE	Kristian Granhaug, Snorre Aunet, Tor Sverre Lande: Body-bias regulator for ultra low power multifunction CMOS gates. ISCAS 2006
15	EE	Yngvar Berg, Omid Mirmotahari, Snorre Aunet: Pseudo Floating-Gate Inverter with Feedback Control. VLSI-SoC 2006: 272-277
2005
14	EE	Valeriu Beiu, Snorre Aunet, Jabulani Nyathi, Ray Robert Rydberg III, Asbjørn Djupdal: On the Advantages of Serial Architectures for Low-Power Reliable Computations. ASAP 2005: 276-281
13	EE	Valeriu Beiu, Artur Zawadski, Razvan Andonie, Snorre Aunet: Using Kolmogorov Inspired Gates for Low Power Nanoelectronics. IWANN 2005: 438-445
12	EE	Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet: Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. IWANN 2005: 486-493
2004
11	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Omid Mirmotahari: Basic Multiple-Valued Functions Using Recharge CMOS Logic. ISMVL 2004: 346-351
2003
10	EE	Snorre Aunet, Morten Hartmann: Real-Time Reconfigurable Linear Threshold Elements and Some Applications to Neural Hardware. ICES 2003: 365-376
9	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Johannes Goplen Lomsdalen, Mats Høvin: Exploiting hyperbolic functions to increase linearity in low-voltage floating-gate transconductance amplifiers. ISCAS (1) 2003: 345-348
8	EE	Yngvar Berg, Snorre Aunet, Omid Mirmotahari, Mats Høvin: Novel recharge semi-floating-gate CMOS logic for multiple-valued systems. ISCAS (5) 2003: 193-196
7	EE	Snorre Aunet, Yngvar Berg: UV-programmable Floating-Gate CMOS Linear Threshold Element "P1N3". IWANN (2) 2003: 57-64
2002
6	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin: A novel floating-gate multiple-valued CMOS full-adder. ISCAS (1) 2002: 877-880
5	EE	Yngvar Berg, Øivind Næss, Snorre Aunet, Renè Jensen, Mats Høvin: Novel floating-gate multiple-valued signal to binary signal converters for multiple-valued CMOS logic. ISCAS (5) 2002: 385-388
4	EE	Trond Ytterdal, Snorre Aunet: Compact low-voltage self-calibrating digital floating-gate CMOS logic circuits. ISCAS (5) 2002: 393-396
2001
3	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin: Extreme low-voltage floating-gate CMOS transconductance amplifier. ISCAS (1) 2001: 37-40
2	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin: Floating-gate CMOS differential analog inverter for ultra low-voltage applications. ISCAS (1) 2001: 9-12
1	EE	Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin: Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. ISCAS (4) 2001: 838-841

Coauthor Index

1	Jon Alfredsson	[19] [20]
2	Håvard Pedersen Alstad	[26] [27]
3	Razvan Andonie	[13]
4	Valeriu Beiu	[12] [13] [14]
5	Yngvar Berg	[1] [2] [3] [5] [6] [7] [8] [9] [11] [15] [22] [25]
6	Hans Kristian Otnes Berge	[21]
7	Tuan Vu Cao	[24] [28]
8	Asbjørn Djupdal	[12] [14]
9	Kristian Granhaug	[16] [17] [18] [23]
10	Henning Gundersen	[3] [22]
11	O. Hagen	[6]
12	Morten Hartmann	[10]
13	Mats Erling Høvin (Mats Høvin)	[1] [2] [3] [5] [6] [8] [9]
14	Renè Jensen	[5] [22]
15	Tor Sverre Lande	[16]
16	Johannes Goplen Lomsdalen	[9] [22] [25]
17	Hamid Mahmoodi (Hamid Mahmoodi-Meimand)	[24] [28]
18	Omid Mirmotahari	[8] [11] [15] [25]
19	Farshad Moradi	[24] [28]
20	Øivind Næss	[1] [2] [3] [5] [6] [9] [11]
21	Jabulani Nyathi	[14]
22	Bengt Oelmann	[19]
23	Ali Peiravi	[28]
24	Ray Robert Rydberg III	[14]
25	Dag T. Wisland	[24] [28]
26	Trond Ytterdal	[4]
27	Artur Zawadski	[13]

Colors in the list of coauthors