2008 |
18 | EE | Jae-Jin Jung,
Kwang-Hyun Baek,
Shin-Il Lim,
Suki Kim,
Sung-Mo Kang:
Design of a 6 bit 1.25 GS/s DAC for WPAN.
ISCAS 2008: 2262-2265 |
17 | EE | Yun-Jeong Kim,
Jong-Ho Lee,
Ja-Hyun Koo,
Kwang-Hyun Baek,
Suki Kim:
6-bit 1.6-GS/s 85-mW Flash Analog to Digital Converter Using Symmetric Three-Input Comparator.
IEICE Transactions 91-C(3): 392-395 (2008) |
2007 |
16 | EE | Chris Masone,
Kwang-Hyun Baek,
Sean Smith:
WSKE: Web Server Key Enabled Cookies.
Financial Cryptography 2007: 294-306 |
15 | EE | Soon-Ik Cho,
Suki Kim,
Shin-Il Lim,
Kwang-Hyun Baek:
A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOS.
ISCAS 2007: 3379-3382 |
14 | EE | Youngkwon Jo,
Hoyoung Park,
Sanghyuk Yang,
Suki Kim,
Kwang-Hyun Baek:
Digitally Controlled Duty Cycle Corrector with 1 ps Resolution.
IEICE Transactions 90-C(9): 1841-1843 (2007) |
2005 |
13 | EE | Bo Hu,
Zhao Li,
Lili Zhou,
C.-J. Richard Shi,
Kwang-Hyun Baek,
Myung-Jun Choe:
Model-compiler based efficient statistical circuit analysis: an industry case study of a 4 GHz/6-bit ADC/DAC/DEMUX ASIC.
ISCAS (6) 2005: 5621-5624 |
12 | EE | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A 32-bit carry lookahead adder using dual-path all-N logic.
IEEE Trans. VLSI Syst. 13(8): 992-996 (2005) |
11 | EE | Edward Merlo,
Kwang-Hyun Baek:
High-Speed Low-Power Small-Area Accumulator Designs for Direct Digital Frequency Synthesizers.
IEICE Transactions 88-A(5): 1373-1378 (2005) |
10 | EE | Kwang-Hyun Baek:
Addressing a High-Speed D/A Converter Design for Mixed-Mode VLSI Systems.
IEICE Transactions 88-C(5): 1053-1060 (2005) |
2004 |
9 | | Ge Yang,
Seong-Ook Jung,
Kwang-Hyun Baek,
Soo Hwan Kim,
Suki Kim,
Sung-Mo Kang:
A low-power 1.85 GHz 32-bit carry lookahead adder using Dual Path All-N-Logic.
ISCAS (2) 2004: 781-784 |
2003 |
8 | EE | Edward Merlo,
Kwang-Hyun Baek,
Myung-Jun Choe:
Exponential split accumulator for high-speed reduced area low-power direct digital frequency synthesizers.
ACM Great Lakes Symposium on VLSI 2003: 249-252 |
7 | EE | Kwang-Hyun Baek,
Myung-Jun Choe,
Edward Merlo,
Sung-Mo Kang:
1-GS/s, 12-bit SiGe BiCMOS D/A converter for high-speed DDFs.
ISCAS (1) 2003: 901-904 |
6 | EE | Kwang-Hyun Baek,
Myung-Jun Choe,
Sung-Mo Kang:
An Efficient Calibration Technique for Systematic Current-Mismatch of D/A Converters.
ISVLSI 2003: 80-86 |
5 | EE | Yong Sin Kim,
Soo Hwan Kim,
Kwang-Hyun Baek,
Suki Kim,
Sung-Mo Kang:
Multiple Trigonometric Approximation of Sine-Amplitude with Small ROM Size for Direct Digital Frequency Synthesizers.
VLSI Design 2003: 261- |
2002 |
4 | EE | Kwang-Hyun Baek,
Myung-Jun Choe,
Sung-Mo Kang:
A low-voltage high-speed BiCMOS current switch with enhanced-spectral performance.
ISCAS (5) 2002: 53-56 |
2001 |
3 | EE | Seung-Moon Yoo,
Chulwoo Kim,
Seong-Ook Jung,
Kwang-Hyun Baek,
Sung-Mo Kang:
New current-mode sense amplifiers for high density DRAM and PIM architectures.
ISCAS (4) 2001: 938-941 |
2000 |
2 | | Ki-Wook Kim,
Kwang-Hyun Baek,
Naresh R. Shanbhag,
C. L. Liu,
Sung-Mo Kang:
Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design.
ICCAD 2000: 318-321 |
1 | EE | Chulwoo Kim,
Jaesik Lee,
Kwang-Hyun Baek,
Eric Martina,
Sung-Mo Kang:
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology.
ICCD 2000: 59-64 |