| 2008 |
|---|
| 20 | EE | Yin-Tsung Hwang,
Wei-Da Chen:
A low complexity complex QR factorization design for signal detection in MIMO OFDM systems.
ISCAS 2008: 932-935 |
| 19 | EE | Jin-Fa Lin,
Yin-Tsung Hwang,
Ming-Hwa Sheu:
Low Complexity Dual-Mode Pulse Generator Designs.
IEICE Transactions 91-A(7): 1812-1815 (2008) |
| 2006 |
|---|
| 18 | EE | Yin-Tsung Hwang,
Jin-Fa Lin,
Ming-Hwa Sheu,
Chia-Jen Sheu:
Low Power Multiplier Designs Based on Improved Column Bypassing Schemes.
APCCAS 2006: 594-597 |
| 17 | EE | Jin-Fa Lin,
Yin-Tsung Hwang,
Ming-Hwa Sheu,
Cheng-Che Ho:
A high speed and energy efficient full adder design using complementary & level restoring carry logic.
ISCAS 2006 |
| 2005 |
|---|
| 16 | EE | Yin-Tsung Hwang,
Chen-Yu Tsai,
Cheng-Chen Lin:
Block-wise adaptive modulation for OFDM WLAN systems.
ISCAS (6) 2005: 6098-6101 |
| 15 | EE | Tai-Yi Huang,
Chung-Ta King,
Youn-Long Steve Lin,
Yin-Tsung Hwang:
The embedded software consortium of taiwan.
ACM Trans. Embedded Comput. Syst. 4(3): 612-632 (2005) |
| 14 | EE | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Yin-Tsung Hwang,
Jun-Hong Chen:
VLSI architectural design tradeoffs for sliding-window log-MAP decoders.
IEEE Trans. VLSI Syst. 13(4): 439-447 (2005) |
| 2004 |
|---|
| 13 | | Chien-Ming Wu,
Ming-Der Shieh,
Chien-Hsing Wu,
Yin-Tsung Hwang,
Jun-Hong Chen,
Hsin-Fu Lo:
VLSI architecture exploration for sliding-window Log-MAP decoders.
ISCAS (2) 2004: 513-516 |
| 12 | EE | Chien-Hsing Wu,
Chien-Ming Wu,
Ming-Der Shieh,
Yin-Tsung Hwang:
High-Speed, Low-Complexity Systolic Designs of Novel Iterative Division Algorithms in GF(2^m).
IEEE Trans. Computers 53(3): 375-380 (2004) |
| 2003 |
|---|
| 11 | EE | Yin-Tsung Hwang,
Kuo-Wei Liao,
Chien-Hsing Wu:
FPGA realization of an OFDM frame synchronization design for dispersive channels.
ISCAS (2) 2003: 256-259 |
| 2002 |
|---|
| 10 | EE | Yin-Tsung Hwang,
Cheng-Ji Chang,
Bor-Liang Chen:
A rapid prototyping embedded system platform and its HW/SW communication interface generation and verification.
APCCAS (1) 2002: 481-484 |
| 9 | EE | Chien-Hsing Wu,
Chien-Ming Wu,
Ming-Der Shieh,
Yin-Tsung Hwang:
An area-efficient systolic division circuit over GF(2/sup m/) for secure communication.
ISCAS (5) 2002: 733-736 |
| 2001 |
|---|
| 8 | EE | Chien-Hsing Wu,
Chien-Ming Wu,
Ming-Der Shieh,
Yin-Tsung Hwang:
Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design.
ISCAS (4) 2001: 33-36 |
| 7 | EE | Yin-Tsung Hwang,
Jih-Cheng Han,
Jing-Yi Liu:
Design and implementation of channel equalizers for block transmission systems.
ISCAS (4) 2001: 354-357 |
| 1998 |
|---|
| 6 | EE | Yin-Tsung Hwang,
Yuan-Hung Wang:
Communication and Interface Synthesis on a Rapid Prototyping Hardware/Software Codesign System.
ISSS 1998: 76-82 |
| 5 | EE | Yin-Tsung Hwang,
Jer-Sho Hwang:
Simulated Evolution Based Parallel Code Generation for Programmable DSP Processors.
J. Inf. Sci. Eng. 14(1): 139-165 (1998) |
| 4 | EE | Yin-Tsung Hwang,
Yuan-Hung Wang,
Jer-Sho Hwang:
Rapid Prototyping of Hardware / Software Codesign for Embedded Signal Processing.
J. Inf. Sci. Eng. 14(3): 605-632 (1998) |
| 1996 |
|---|
| 3 | EE | Ching-Long Su,
Yin-Tsung Hwang:
Distributed arithmetic-based architectures for high speed IIR filter design.
ICPADS 1996: 156-161 |
| 1995 |
|---|
| 2 | EE | Yin-Tsung Hwang,
Yu Hen Hu:
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays.
VLSI Signal Processing 11(1-2): 133-150 (1995) |
| 1992 |
|---|
| 1 | EE | Yin-Tsung Hwang,
Yu Hen Hu:
MSSM - A design aid for multi-stage systolic mapping.
VLSI Signal Processing 4(2-3): 125-145 (1992) |
