S. M. Aziz

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8EES. Raghunath, S. M. Aziz: Design of an Area Efficient High-Speed Color FDWT Processor. APCCAS 2006: 474-477
7EES. M. Aziz, S. J. Carr: On C-Testability of Carry Free Dividers. DELTA 2002: 417-424
6EES. M. Aziz, C. N. Basheer, Joarder Kamruzzaman: A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier. DELTA 2002: 504-506
5EEA. B. M. Harun-ur Rashid, M. Karim, S. M. Aziz: Testing complementary pass-transistor logic circuits. ISCAS (4) 2001: 5-8
4EES. M. Aziz, Joarder Kamruzzaman: Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. Asian Test Symposium 1998: 119-
3EES. M. Aziz: A C-testable modified Booth's array multiplier. VLSI Design 1995: 278-282
2 S. M. Aziz, W. A. J. Waller: On Testability of Differential Split-Level CMOS Circuits. VLSI Design 1994: 191-196
1 W. A. J. Waller, S. M. Aziz: A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic. VLSI 1993: 133-142

Coauthor Index

1C. N. Basheer [6]
2S. J. Carr [7]
3Joarder Kamruzzaman [4] [6]
4M. Karim [5]
5S. Raghunath [8]
6A. B. M. Harun-ur Rashid [5]
7W. A. J. Waller [1] [2]

Colors in the list of coauthors

Copyright © Sun May 17 03:24:02 2009 by Michael Ley (ley@uni-trier.de)