S. M. Aziz

2006
8	EE	S. Raghunath, S. M. Aziz: Design of an Area Efficient High-Speed Color FDWT Processor. APCCAS 2006: 474-477
2002
7	EE	S. M. Aziz, S. J. Carr: On C-Testability of Carry Free Dividers. DELTA 2002: 417-424
6	EE	S. M. Aziz, C. N. Basheer, Joarder Kamruzzaman: A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier. DELTA 2002: 504-506
2001
5	EE	A. B. M. Harun-ur Rashid, M. Karim, S. M. Aziz: Testing complementary pass-transistor logic circuits. ISCAS (4) 2001: 5-8
1998
4	EE	S. M. Aziz, Joarder Kamruzzaman: Fault Characterization of Low Capacitance Full-Swing BiCMOS Logic Circuits. Asian Test Symposium 1998: 119-
1995
3	EE	S. M. Aziz: A C-testable modified Booth's array multiplier. VLSI Design 1995: 278-282
1994
2		S. M. Aziz, W. A. J. Waller: On Testability of Differential Split-Level CMOS Circuits. VLSI Design 1994: 191-196
1993
1		W. A. J. Waller, S. M. Aziz: A C-testable parallel multiplier using differential cascode voltage switch (DDVS) logic. VLSI 1993: 133-142

Coauthor Index

1	C. N. Basheer	[6]
2	S. J. Carr	[7]
3	Joarder Kamruzzaman	[4] [6]
4	M. Karim	[5]
5	S. Raghunath	[8]
6	A. B. M. Harun-ur Rashid	[5]
7	W. A. J. Waller	[1] [2]

Colors in the list of coauthors